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 FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM44-10105-2E
2MC-16LX F
FAMILY
16-BIT MICROCONTROLLER
MB90590 SERIES HARDWARE MANUAL
2MC-16LX F
FAMILY
16-BIT MICROCONTROLLER
MB90590 SERIES HARDWARE MANUAL
FUJITSU LIMITED
PREFACE
s Objectives and Intended Reader Thank you very much for your continued patronage of Fujitsu semiconductor products. The MB90590 series has been developed as a general-purpose version of the F2MC(R)-16LX series, which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC (ASIC). This manual explains the functions and operation of the MB90590 series for designers who actually use the MB90590 series to design products. Read this manual first. s Trademarks F2MC stands for FUJITSU Flexible Microcontroller and is a registered trademark of Fujitsu Limited. s Structure of This Manual Chapter 1 Overview Chapter 1 explains the advantages and basic specifications of the MB90590 series. Chapter 2 CPU Chapter 2 explains the memory layout of the MB90590 series. Chapter 3 Interrupts Chapter 3 explains the interrupt functions of the MB90590 series and also explains the functions and operation of the extended intelligent I/O service (EI2OS). Chapter 4 Delayed Interrupts Chapter 4 explains the delayed interrupt functions and operation. Chapter 5 Clock and Reset Chapter 5 explains the clock and reset functions and operation. Chapter 6 Low-Power Control Circuit Chapter 6 explains the functions and operation of the low-power control circuit. Chapter 7 Memory Access Modes Chapter 7 explains the functions and operation of the memory access modes. Chapter 8 I/O Ports Chapter 8 explains the I/O port functions and operation. Chapter 9 Time Base Timer This chapter explains the time base timer functions and operation. Chapter 10 Watchdog Timer Chapter 10 explains the watchdog timer functions and operation. Chapter 11 16-bit I/O Timer Chapter 11 explains the 16-bit I/O timer functions and operation.
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Chapter 12 16-bit Reload Timer (with Event Count Function) Chapter 12 explains functions and operation of the 16-bit reload timer (with the event count function). Chapter 13 Time Base Timer Chapter 13 explains the time base timer functions and operation. Chapter 14 8/16-bit PPG Chapter 14 explains the 8/16-bit PPG functions and operation. Chapter 15 DTP/External Interrupts Chapter 15 explains the DTP/external interrupt functions and operation. Chapter 16 A/D Converter Chapter 16 explains the A/D converter functions and operation. Chapter 17 UART0 Chapter 17 explains the UART0 functions and operation. Chapter 18 Serial I/O Chapter 18 explains the serial I/O functions and operation. Chapter 19 CAN Controller Chapter 19 explains the CAN controller functions and operation. Chapter 20 Stepping Motor Controller Chapter 20 explains the functions and operation of the stepping motor controller. Chapter 21 Sound Generator Chapter 21 explains sound generator functions and operation. Chapter 22 ROM Correction Chapter 22 explains the ROM correction functions and operation. Chapter 23 ROM Mirroring Function Selection Module Chapter 23 explains the functions and operation of the ROM mirroring function selection module. Chapter 24 Two-megabit Flash Memory Chapter 24 explains the functions and operation of the 2-megabit flash memory. Chapter 25 Example of Connection F2MC-16LX MB90F594A for Serial Writing Chapter 25 explains the connection of F2MC-16LX MB90F594A for serial writing, using an example. Appendix Appendix explains instructions, provides I/O maps and timing diagrams in flash memory mode, and lists MB90590 interrupt vectors.
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1. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 2. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 3. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. 4. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 5. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. 6. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
(c)1999 FUJITSU LIMITED Printed in Japan
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READING THIS MANUAL
s Page organization Each section in this document contains a summary of the section. Reading only the summaries will give you an overview of the product. In addition, the title of the section is also appears in subsections so that you always know which section you are reading.
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CONTENT
CHAPTER 1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
OVERVIEW ................................................................................................... 1
Product Overview .................................................................................................................................. 2 Features ................................................................................................................................................ 3 Block Diagram ....................................................................................................................................... 5 Pin Assignment ...................................................................................................................................... 6 Package Dimensions ............................................................................................................................. 7 Pin Functions ......................................................................................................................................... 8 Input-Output Circuits ............................................................................................................................ 12 Handling the Device ............................................................................................................................. 15
CHAPTER 2
CPU ............................................................................................................. 17
2.1 Outline of CPU ..................................................................................................................................... 18 2.2 Memory Space ..................................................................................................................................... 19 2.3 Memory Space Map ............................................................................................................................. 20 2.4 Linear Addressing ................................................................................................................................ 21 2.5 Bank Addressing Types ....................................................................................................................... 22 2.6 Multi-byte Data in Memory Space ........................................................................................................ 24 2.7 Registers .............................................................................................................................................. 25 2.7.1 Accumulator (A) .............................................................................................................................. 27 2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................... 28 2.7.3 Processor Status (PS) .................................................................................................................... 29 2.7.4 Program Counter (PC) .................................................................................................................... 32 2.8 Register Bank ...................................................................................................................................... 33 2.9 Prefix Codes ........................................................................................................................................ 35 2.10 Interrupt Disable Instructions ............................................................................................................... 37
CHAPTER 3
INTERRUPTS .............................................................................................. 39
3.1 Outline of Interrupts ............................................................................................................................. 40 3.2 Interrupt Vector .................................................................................................................................... 43 3.3 Interrupt Control Registers (ICR) ......................................................................................................... 44 3.4 Interrupt Flow ....................................................................................................................................... 47 3.5 Hardware Interrupts ............................................................................................................................. 49 3.5.1 Hardware Interrupt Operation ......................................................................................................... 50 3.5.2 Occurrence and Release of Hardware Interrupt ............................................................................. 51 3.5.3 Multiple interrupts ........................................................................................................................... 53 3.6 Software Interrupts .............................................................................................................................. 54 3.7 Extended Intelligent I/O Service (EI2OS) ............................................................................................. 56 3.7.1 Extended Intelligent I/O Service Descriptor (ISD) .......................................................................... 58 3.7.2 EI2OS Status Register (ISCS) ........................................................................................................ 60 3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) ................. 61 3.9 Exceptions ........................................................................................................................................... 64
CHAPTER 4
4.1
DELAYD INTERRUPT ................................................................................ 65
Outline of Delayed Interrupt Module .................................................................................................... 66 v
4.2 4.3
Delayed Interrupt Register .................................................................................................................. 67 Delayed Interrupt Operation ................................................................................................................ 68
CHAPTER 5
5.1 5.2 5.3
CLOCK AND RESET .................................................................................. 69
Clock Generator .................................................................................................................................. 70 Reset Cause Occurrence .................................................................................................................... 71 Reset Causes ..................................................................................................................................... 73
CHAPTER 6
LOW-POWER CONTORL CIRCUIT ........................................................... 75
76 78 79 81 83 85 86 87 89 90 91 92
6.1 Outline of Low-Power Control Circuit .................................................................................................. 6.2 Registers ............................................................................................................................................. 6.2.1 Low Power Mode Control Register (LPMCR) ................................................................................ 6.2.2 Clock Selection Register (CKSCR) ................................................................................................ 6.3 Low-Power Mode Operation ............................................................................................................... 6.3.1 Sleep Mode .................................................................................................................................... 6.3.2 Timer Mode .................................................................................................................................... 6.3.3 Stop Mode ..................................................................................................................................... 6.3.4 Hardware Standby Mode ............................................................................................................... 6.4 Intermittent CPU Operation ................................................................................................................. 6.5 Switching Machine Clocks .................................................................................................................. 6.6 Status Transition of Clock Selection ...................................................................................................
CHAPTER 7
7.1 7.2 7.3
MEMORY ACCESS MODES ...................................................................... 93
Outline of Memory Access Modes ...................................................................................................... 94 Mode Pins ........................................................................................................................................... 95 Mode Data .......................................................................................................................................... 96
CHAPTER 8
I/O PORTS .................................................................................................. 99
100 101 102 103 104
8.1 I/O Ports ............................................................................................................................................ 8.2 I/O Port Registers ............................................................................................................................. 8.2.1 Port Data Register ....................................................................................................................... 8.2.2 Port Direction Register ................................................................................................................. 8.2.3 Analog Input Enable Register .....................................................................................................
CHAPTER 9
9.1 9.2 9.3
TIME BASE TIMER ................................................................................ 105
Outline of Time Base Timer .............................................................................................................. 106 Time Base Timer Control Register .................................................................................................... 107 Operations of Time Base Timer ........................................................................................................ 109
CHAPTER 10 WATCH-DOG TIMER ................................................................................ 111
10.1 Outline of Watch-Dog Timer ............................................................................................................. 112 10.2 Watch-dog Timer Operation .............................................................................................................. 115
CHAPTER 11 16-BIT I/O TIMER ..................................................................................... 117
11.1 Outline of 16-Bit I/O Timer ................................................................................................................ 11.2 16-Bit I/O Timer Registers ................................................................................................................ 11.3 16-bit Free-running Timer ................................................................................................................. 11.3.1 Data Register ............................................................................................................................... vi 118 120 121 122
11.3.2 Control Status Register ................................................................................................................ 123 11.3.3 16-bit Free-running TimerOperation ............................................................................................. 125 11.4 Output Compare ................................................................................................................................ 127 11.4.1 Output Compare Register ............................................................................................................. 128 11.4.2 Control Status Register of Output Compare ................................................................................. 129 11.4.3 16-bit Output Compare Operation ................................................................................................ 132 11.5 Input Capture ..................................................................................................................................... 135 11.5.1 Input Capture Register Details ..................................................................................................... 136 11.5.2 16-bit Input Capture Operation ..................................................................................................... 138
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ............... 141
12.1 Outline of 16-Bit Reload Timer (with Event Count Function) ............................................................. 142 12.2 16-Bit Reload Timer (with Event Count Function) ............................................................................. 144 12.2.1 Timer Control Status Register (TMCSR) ...................................................................................... 145 12.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) ...................... 148 12.3 Internal Clock and External Clock Operations of 16-bit Reload Timer .............................................. 149 12.4 Underflow Operation of 16-bit Reload Timer ..................................................................................... 152 12.5 Output Pin Functions of 16-bit Reload Timer ..................................................................................... 153 12.6 Counter Operation State .................................................................................................................... 154
CHAPTER 13 WATCH-DOG TIMER ................................................................................ 155
13.1 Outline of Watch Timer ...................................................................................................................... 156 13.2 Watch-dog Timer Registers ............................................................................................................... 157 13.2.1 Timer Control Register ................................................................................................................. 158 13.2.2 Sub-second Registers .................................................................................................................. 160 13.2.3 Second/Minute/Hour Registers ..................................................................................................... 161
CHAPTER 14 8/16-BIT PPG ............................................................................................ 163
14.1 Outline of 8/16-bit PPG ...................................................................................................................... 164 14.2 Block Diagram of 8/16-Bit PPG ......................................................................................................... 165 14.3 8/16-Bit PPG Registers ...................................................................................................................... 167 14.3.1 PPG0 Operation Mode Control Register (PPGC0) ....................................................................... 168 14.3.2 PPG1 Operation Mode Control Register (PPGC1) ....................................................................... 170 14.3.3 PPG0, 1 Output Control Register (PPG01) .................................................................................. 172 14.3.4 Reload Register (PRLL/PRLH) ..................................................................................................... 174 14.4 Operations of 8/16-bit PPG ................................................................................................................ 175 14.5 Selecting a Count Clock for 8/16-Bit PPG ......................................................................................... 177 14.6 Controlling Pin Output of 8/16-bit PPG Pulses .................................................................................. 178 14.7 8/16-bit PPG Interrupts ...................................................................................................................... 179 14.8 Initial Values of 8/16-bit PPG Hardware ............................................................................................ 180
CHAPTER 15 DTP/EXTERNAL INTERRUPTS ............................................................... 183
15.1 15.2 15.3 15.4 15.5 Outline of DTP/External Interrupts ..................................................................................................... 184 DTP/External Interrupt Registers ....................................................................................................... 186 Operations of DTP/External Interrupts ............................................................................................... 188 Switching between External Interrupt and DTP Requests ................................................................. 190 Notes on Using DTP/External Interrupts ............................................................................................ 191
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CHAPTER 16 A/D Converter .......................................................................................... 193
16.1 Features of A/D Converter ................................................................................................................ 16.2 Block Diagram of A/D Converter ....................................................................................................... 16.3 A/D Converter Registers ................................................................................................................... 16.3.1 Control Status Registers (ADCS0) ............................................................................................... 16.3.2 Control Status Register (ADCS1) ................................................................................................ 16.3.3 Data Registers (ADCR1 and ADCR0) ......................................................................................... 16.4 Operations of A/D Converter ............................................................................................................. 16.5 Conversion Using EI2OS .................................................................................................................. 16.5.1 Starting EI2OS in Single Mode ................................................................................................... 16.5.2 Starting EI2OS in Continuous Mode ............................................................................................ 16.5.3 Starting EI2OS in Stop Mode ....................................................................................................... 16.6 Conversion Data Protection .............................................................................................................. 194 196 197 198 201 204 206 208 209 211 213 215
CHAPTER 17 UART0 ...................................................................................................... 217
17.1 Feature of UART0 ............................................................................................................................. 17.2 UART Block Diagram ........................................................................................................................ 17.3 UART Registers ................................................................................................................................ 17.3.1 Serial Mode Control Register (UMC) ........................................................................................... 17.3.2 Status Register (USR) ................................................................................................................. 17.3.3 Input Data Register (UIDR) and Output Data Register (UODR) .................................................. 17.3.4 Rate and Data Register (URD) .................................................................................................... 17.4 UART0 Operation ............................................................................................................................. 17.5 Baud Rate ......................................................................................................................................... 17.6 Internal and External Clock ............................................................................................................... 17.7 Transfer Data Format ........................................................................................................................ 17.8 Parity Bit ............................................................................................................................................ 17.9 Interrupt Generation and Flag Set Timings ....................................................................................... 17.9.1 Flag Set Timings for a Receive Operation (in Mode 0, 1, or 3) .................................................... 17.9.2 Flag set timings for a receive operation (in mode 2) .................................................................... 17.9.3 Flag set Timings for a Transmit Operation ................................................................................... 17.9.4 Status Flag During Transmit and Receive Operation .................................................................. 17.10 UART0 Application Example ............................................................................................................. 218 219 220 221 223 225 226 228 229 232 233 234 235 236 237 238 239 241
CHAPTER 18 SERIAL I/O ............................................................................................... 243
18.1 Outline of Serial I/O ........................................................................................................................... 18.2 Serial I/O Registers ........................................................................................................................... 18.2.1 Serial Mode Control Status Register (SMCS) .............................................................................. 18.2.2 Serial Shift Data Register (SDR) .................................................................................................. 18.3 Serial I/O Prescaler (CDCR) ............................................................................................................. 18.4 Serial I/O Operation .......................................................................................................................... 18.4.1 Shift Clock .................................................................................................................................... 18.4.2 Serial I/O Operation ..................................................................................................................... 18.4.3 Shift Operation Start/Stop Timing ................................................................................................ 18.4.4 Interrupt Function of the Extended Serial I/O Interface ............................................................... 18.5 Negative Clock Operation ................................................................................................................. 244 245 246 250 251 252 253 254 256 258 259
CHAPTER 19 CAN CONTROLLER ................................................................................. 261
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19.1 Features of CAN Controller ............................................................................................................... 262 19.2 Block Diagram of CAN Controller ...................................................................................................... 263 19.3 List of Overall Control Registers ........................................................................................................ 264 19.4 List of Message Buffers (ID Registers) .............................................................................................. 266 19.5 List of Message Buffers (DLC Registers and Data Registers) ........................................................... 269 19.6 Classifying the CAN Controller Registers .......................................................................................... 273 19.6.1 Control Status Register (CSR) ..................................................................................................... 274 19.6.2 Bus Operation Stop Bit (HALT = 1) .............................................................................................. 277 19.6.3 Last Event Indicator Register (LEIR) ............................................................................................ 278 19.6.4 Receive and Transmit Error Counters (RTEC) ............................................................................. 280 19.6.5 Bit Timing Register (BTR) ............................................................................................................. 281 19.6.6 Message Buffer Valid Register (BVALR) ...................................................................................... 283 19.6.7 IDE register (IDER) ....................................................................................................................... 284 19.6.8 Transmission Request Register (TREQR) ................................................................................... 285 19.6.9 Transmission RTR Register (TRTRR) .......................................................................................... 286 19.6.10 Remote Frame Receiving Wait Register (RFWTR) ...................................................................... 287 19.6.11 Transmission Cancel Register (TCANR) ...................................................................................... 288 19.6.12 Transmission Complete Register (TCR) ....................................................................................... 289 19.6.13 Transmission Interrupt Enable Register (TIER) ............................................................................ 290 19.6.14 Reception Complete Register (RCR) ........................................................................................... 291 19.6.15 Remote Request Receiving Register (RRTRR) ........................................................................... 292 19.6.16 Receive Overrun Register (ROVRR) ............................................................................................ 293 19.6.17 Reception Interrupt Enable Register (RIER) ................................................................................ 294 19.6.18 Acceptance Mask Select Register (AMSR) .................................................................................. 295 19.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) ............................................................. 297 19.6.20 Message Buffers ........................................................................................................................... 299 19.6.21 ID Register x (x = 0 to 15) (IDRx) ................................................................................................. 300 19.6.22 DLC Register x (x = 0 to 15) (DLCRx) .......................................................................................... 302 19.6.23 Data Register x (x = 0 to 15) (DTRx) ............................................................................................ 303 19.7 Transmission of CAN Controller ........................................................................................................ 305 19.8 Reception of CAN Controller ............................................................................................................. 307 19.9 Reception Flowchart of CAN Controller ............................................................................................. 310 19.10 How to Use the CAN Controller ......................................................................................................... 311 19.11 Procedure for Transmission by Message Buffer (x) .......................................................................... 313 19.12 Procedure for Reception by Message Buffer (x) ................................................................................ 315 19.13 Setting Configuration of Multi-level Message Buffer .......................................................................... 317
CHAPTER 20 STEPPING MOTOR CONTROLLER ........................................................ 319
20.1 Outline of Stepping Motor Controller ................................................................................................. 320 20.2 Stepping Motor Controller Registers .................................................................................................. 321 20.2.1 PWM Control 0 register ................................................................................................................ 322 20.2.2 PWM1&2 Compare Registers ...................................................................................................... 323 20.3 PWM1&2 Select Registers ................................................................................................................ 324
CHAPTER 21 SOUND GENERATOR .............................................................................. 327
21.1 Outline of Sound Generator ............................................................................................................... 328 21.2 Sound Generator Registers ............................................................................................................... 329 21.2.1 Sound Control Register ................................................................................................................ 330
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21.2.2 21.2.3 21.2.4 21.2.5
Frequency Data register .............................................................................................................. Amplitude Data Register .............................................................................................................. Decrement Grade Register .......................................................................................................... Tone Count Register ....................................................................................................................
332 333 334 335
CHAPTER 22 ROM CORRECTION ................................................................................. 337
22.1 Outline of ROM Correction ................................................................................................................ 22.2 Application Example of ROM Correction .......................................................................................... 22.2.1 Correction Example of Program Errors ........................................................................................ 22.2.2 Example of Correction Processing ............................................................................................... 338 340 341 342
CHAPTER 23 ROM MIRRORING MODULE .................................................................... 345
23.1 Outline of ROM Mirroring Module ..................................................................................................... 346 23.2 ROM Mirroring Register (ROMM) ..................................................................................................... 347
CHAPTER 24 2M/3M-BIT FLASH MEMORY .................................................................. 349
24.1 Outline of 2M/3M-Bit Flash Memory ................................................................................................. 24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory ............ 24.3 Write/Erase Modes ........................................................................................................................... 24.4 Flash Memory Control Status Register (FMCS) ............................................................................... 24.5 Starting the Flash Memory Automatic Algorithm ............................................................................... 24.6 Confirming the Automatic Algorithm Execution State ....................................................................... 24.6.1 Data Polling Flag (DQ7) ............................................................................................................... 24.6.2 Toggle Bit Flag (DQ6) .................................................................................................................. 24.6.3 Timing Limit Exceeded Flag (DQ5) .............................................................................................. 24.6.4 Sector Erase Timer Flag (DQ3) ................................................................................................... 24.7 Detailed Explanation of Writing to and Erasing Flash Memory ......................................................... 24.7.1 Setting The Read/Reset State ..................................................................................................... 24.7.2 Writing Data ................................................................................................................................. 24.7.3 Erasing All Data (Erasing Chips) ................................................................................................. 24.7.4 Erasing Optional Data (Erasing Sectors) ..................................................................................... 24.7.5 Suspending Sector Erase ............................................................................................................ 24.7.6 Restarting Sector Erase ............................................................................................................... 24.8 Notes on using 2M-Bit Flash Memory ............................................................................................... 24.9 Reset Vector Address in Flash Memory ........................................................................................... 24.10 Example of Programming 2M/3M-Bit Flash Memory ........................................................................ 350 351 353 355 357 358 360 362 363 364 365 366 367 369 370 372 373 374 376 377
CHAPTER 25 EXAMPLES OF F2MC-16LX MB90F591/MB90F594A SERIAL WRITE CONNECTION .......................................................................................... 381
25.1 25.2 25.3 25.4 Basic Configuration of F2MC-16LX MB90F591/MB90F594A Serial Write Connection .................... 382 Example of Serial Write Connection (User Power Supply Used) ...................................................... 385 Example of Serial Write Connection (Power Supplied from the Writer) ............................................ 387 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used) ................................................................................................................................................ 389 25.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Writer) ............................................................................................................................................... 391
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APPENDIX .......................................................................................................................... 393
APPENDIX A I/O Maps ............................................................................................................................ 394 APPENDIX B INSTRUCTIONS ................................................................................................................ 404 B.1 Instruction Types ............................................................................................................................. 405 B.2 Addressing ...................................................................................................................................... 406 B.3 Direct Addressing ............................................................................................................................ 408 B.4 Indirect Addressing ......................................................................................................................... 413 B.5 Execution Cycle Count .................................................................................................................... 419 B.6 Effective Address Field ................................................................................................................... 422 B.7 How to Read the Instruction List ..................................................................................................... 424 B.8 F2MC-16LX Instruction List ............................................................................................................. 427 B.9 Instruction Map ................................................................................................................................ 438 APPENDIX C Timing Diagrams in Flash Memory Mode .......................................................................... 460 APPENDIX D List of MB90590 Interrupt Vectors ..................................................................................... 465
INDEX ................................................................................................................................. 469
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FIGURES
Figure 1.3-1 Figure 1.4-1 Figure 1.5-1 Figure 1.8-1 Figure 1.8-2 Figure 2.2-1 Figure 2.3-1 Figure 2.4-1 Figure 2.4-2 Figure 2.5-1 Figure 2.6-1 Figure 2.6-2 Figure 2.7-1 Figure 2.7-2 Figure 2.7-3 Figure 2.7-4 Figure 2.7-5 Figure 2.7-6 Figure 2.7-7 Figure 2.7-8 Figure 2.7-9 Figure 2.7-10 Figure 2.8-1 Figure 2.10-1 Figure 2.10-2 Figure 2.10-3 Figure 3.1-1 Figure 3.1-2 Figure 3.1-3 Figure 3.3-1 Figure 3.4-1 Figure 3.4-2 Figure 3.5-1 Figure 3.5-2 Figure 3.6-1 xii
Block Diagram ............................................................................................................................ 5 Pin Assignment ........................................................................................................................... 6 Package Dimensions .................................................................................................................. 7 Using External Clock ................................................................................................................ 15 Power Supply Pins (Vcc/Vss) ................................................................................................... 16 Sample Relationship between F2MC-16LX System and Memory Map .................................... 19 Memory Space Map .................................................................................................................. 20 Example of Linear Method (24-bit Register Operand Specification) ......................................... 21 Example of Linear Method (32-bit Register Indirect Specification) ........................................... 21 Physical Addresses of Each Space .......................................................................................... 23 Sample Allocation of Multi-byte Data in Memory ...................................................................... 24 Execution of MOVW A, 080FFFFH ........................................................................................... 24 Special Registers ...................................................................................................................... 26 General-purpose Registers ....................................................................................................... 26 32-bit Data Transfer .................................................................................................................. 27 AL-AH Transfer ......................................................................................................................... 27 Stack Manipulation Instruction and Stack Pointer .................................................................... 28 Processor Status (PS) Structure ............................................................................................... 29 Condition Code Register (CCR) Configuration ......................................................................... 29 Register Bank Pointer (RP) ...................................................................................................... 30 Interrupt Level Register (ILM) ................................................................................................... 30 Program Counter ...................................................................................................................... 32 Generating a Physical address in Direct Addressing Mode ...................................................... 34 Interrupt Disable Instruction ...................................................................................................... 37 Interrupt Disable Instructions and Prefix Codes ....................................................................... 37 Consecutive Prefix Codes ........................................................................................................ 37 Overview of Hardware Interrupts .............................................................................................. 40 Overview of Software Interrupts ............................................................................................... 41 Overview of the Extended Intelligent I/O Service (EI2OS) ........................................................ 42 Interrupt Control Register (ICR) ................................................................................................ 44 Interrupt Flow ............................................................................................................................ 47 Register Saving during Interrupt Processing ............................................................................ 48 Occurrence and Release of Hardware Interrup ........................................................................ 51 Registers Saved in Stack .......................................................................................................... 53 Occurrence and Release of Software Interrupt ........................................................................ 55
Figure 3.7-1 Figure 3.7-2 Figure 3.7-3 Figure 3.7-4 Figure 3.7-5 Figure 3.8-1 Figure 3.8-2 Figure 4.1-1 Figure 4.3-1 Figure 5.1-1 Figure 5.2-1 Figure 5.3-1 Figure 5.3-2 Figure 6.1-1 Figure 6.4-1 Figure 6.6-1 Figure 7.3-1 Figure 7.3-2 Figure 8.1-1 Figure 8.2-1 Figure 8.2-2 Figure 8.2-3 Figure 8.2-4 Figure 9.1-1 Figure 10.1-1 Figure 10.2-1 Figure 11.1-1 Figure 11.3-1 Figure 11.4-1 Figure 11.4-2 Figure 11.4-3 Figure 11.5-1 Figure 11.5-2 Figure 12.1-1 Figure 12.3-1 Figure 12.3-2 Figure 12.3-3 Figure 12.4-1
Outline of Extended Intelligent I/O Service ................................................................................ 57 Extended Intelligent I/O Service Descriptor Configuration ........................................................ 58 Data Counter Configuration ....................................................................................................... 58 I/O Register Address Pointer Configuration .............................................................................. 59 ISCS Configuration .................................................................................................................... 60 EI2OS Operation Flow ............................................................................................................... 61 EI2OS Use Flow ........................................................................................................................ 62 Block Diagram ........................................................................................................................... 66 Delayed Interrupt Issuance ........................................................................................................ 68 Clock Generator Circuit Block Diagram ..................................................................................... 70 Source and Destination of Reset Vector and Mode Data .......................................................... 72 Reset Cause bit Block Diagram ................................................................................................. 74 WDTC (Watch-Dog Timer Control) Register ............................................................................. 74 Low-power Control Circuit and Clock Generator ....................................................................... 77 Intermittent CPU Operation ....................................................................................................... 90 Status Transition of Clock Selection .......................................................................................... 92 Mode Data Structure ................................................................................................................. 96 Access Areas and Physical Addresses in each Bus Mode ....................................................... 97 I/O Port Block Diagram ............................................................................................................ 100 I/O Port Registers .................................................................................................................... 101 Port Data Registers ................................................................................................................. 102 Port Direction Registers ........................................................................................................... 103 Analog Input Enable Register .................................................................................................. 104 Block Diagram of Time Base Timer ......................................................................................... 106 Watch-dog Timer Block Diagram ............................................................................................. 112 Watch-dog Timer Operation .................................................................................................... 115 Block Diagram of 16-bit I/O Timer ........................................................................................... 119 16-bit Free-running Timer Block Diagram ............................................................................... 121 Output Compare Block Diagram .............................................................................................. 127 Sample of Output Waveform when Compare Registers 0 and 1 are Used ............................. 132 Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is '0') 133 Input Capture Block Diagram .................................................................................................. 135 Sample of Input Capture Fetch Timing .................................................................................... 138 Block Diagram of 16-bit Reload Timer ..................................................................................... 143 Activation and Operation of 16-bit Reload Timer Counter ....................................................... 149 Trigger Input Operation of 16-bit Reload Timer ....................................................................... 150 Gate Input Operation of 16-bit Reload Timer .......................................................................... 150 Underflow Operation of 16-bit Reload Timer ........................................................................... 152
xiii
Figure 12.5-1 Figure 12.5-2 Figure 12.6-1 Figure 13.1-1 Figure 14.2-1 Figure 14.2-2 Figure 14.4-1 Figure 14.6-1 Figure 14.8-1 Figure 14.8-2 Figure 15.1-1 Figure 15.3-1 Figure 15.3-2 Figure 15.3-3 Figure 15.4-1 Figure 15.5-1 Figure 15.5-2 Figure 16.2-1 Figure 16.3-1 Figure 16.5-1 Figure 17.2-1 Figure 17.7-1 Figure 17.8-1 Figure 17.9-1 Figure 17.9-2 Figure 17.9-3 Figure 17.9-4 Figure 17.9-5 Figure 17.9-6 Figure 17.9-7 Figure 17.9-8
Output Pin Function of 16-bit Reload Timer (1) ...................................................................... 153 Output Pin Function of 16-bit Reload Timer (2) ...................................................................... 153 Counter State Transitions ....................................................................................................... 154 Block Diagram of Watch-dog Timer ........................................................................................ 156 8-bit PPG ch0 Block Diagram ................................................................................................. 165 8-bit PPG ch1 Block Diagram ................................................................................................. 166 PPG Output Operation, Output Waveform ............................................................................. 176 8+8 PPG Output Operation Waveform ................................................................................... 178 Write Timing for 8/16-bit PPG Reload Registers (PRLL and PRLH) ...................................... 180 PRL Write Operation Block Diagram ...................................................................................... 181 Block Diagram of DTP/External Interrupts .............................................................................. 184 External Interrupt .................................................................................................................... 188 Timing to Cancel the External Interrupt at the End of DTP Operation .................................... 189 Sample Interface to the External Peripheral ........................................................................... 189 Switching Between External Interrupt and DTP Requests ..................................................... 190 Clearing the Cause Hold Circuit Upon Level Set .................................................................... 192 Interrupt Cause and Interrupt Request to the Interrupt Controller While Interrupts are Enabled ............................................................................................................................ 192 Block Diagram of A/D Converter ............................................................................................. 196 A/D Converter Register Configuration .................................................................................... 197 A/D conversion processing flow from the start to converted data transfer (in continuous mode) ...................................................................................................................................... 208 UART Block Diagram .............................................................................................................. 219 Transfer Data Format ............................................................................................................. 233 Serial Data with Parity Enabled .............................................................................................. 234 RDRF Set Timing (Mode 0, 1, or 3) ........................................................................................ 236 ORFE Set Timing (Mode 0, 1, or 3) ........................................................................................ 236 PE Set Timing (Mode 0, 1, or 3) ............................................................................................. 236 RDRF Set Timing (Mode 2) .................................................................................................... 237 ORFE Set Timing (Mode 2) .................................................................................................... 237 TDRE Set Timing (Mode 0) .................................................................................................... 238 RBF Set Timing (Mode 0) ....................................................................................................... 239 TBF Set Timing (Mode 0) ....................................................................................................... 239
Figure 17.10-1 RBF Set Timing (mode 0) ....................................................................................................... 241 Figure 17.10-2 Example System Configuration Using Mode 2 ....................................................................... 241 Figure 17.10-3 Communication Flowchart for Mode 2 Operation ................................................................... 242 Figure 18.1-1 Figure 18.4-1 Figure 18.4-2 xiv Extended Serial I/O Interface Block Diagram ......................................................................... 244 Extended I/O Serial Interface Operation Transitions .............................................................. 255 Serial Data Register Read/write ............................................................................................. 255
Figure 18.4-3 Figure 18.4-4 Figure 18.4-5 Figure 18.4-6 Figure 18.4-7 Figure 18.4-8 Figure 19.2-1 Figure 19.6-1 Figure 19.6-2 Figure 19.6-3 Figure 19.7-1 Figure 19.8-1 Figure 19.9-1
Shift Operation Start/Stop Timing (Internal Clock) .................................................................. 256 Shift Operation Start/Stop Timing (External Clock) ................................................................. 256 Shift Operation Start/Stop Timing (External Shift Clock Mode with Instruction Shift) .............. 257 Stop Timing when '1' is Written to the STOP Bit ..................................................................... 257 Serial Data I/O Shift Timing ..................................................................................................... 257 Interrupt Signal Output Timing of the Extended Serial I/O Interface ....................................... 258 Block Diagram of CAN Controller ............................................................................................ 263 Node Status Transition Diagram ............................................................................................. 275 Bit Time Segment in CAN Specification .................................................................................. 282 Bit Time Segment in CAN Controller ....................................................................................... 282 Transmission Flowchart of the CAN Controller ....................................................................... 306 Flowchart Determining Message Buffer (x) where Received Messages Stored ..................... 308 Reception Flowchart of the CAN Controller ............................................................................. 310
Figure 19.12-1 Example of Receive Interrupt Handling ................................................................................... 316 Figure 19.13-1 Examples of Operation of Multi-level Message Buffer ............................................................. 318 Figure 20.1-1 Figure 21.1-1 Figure 21.2-1 Figure 21.2-2 Figure 22.1-1 Figure 22.2-1 Figure 22.2-2 Figure 22.2-3 Figure 22.2-4 Figure 23.1-1 Figure 24.2-1 Figure 24.2-2 Figure 24.7-1 Figure 24.7-2 Figure 25.2-1 Figure 25.3-1 Figure 25.4-1 Figure 25.5-1 Figure B.3-1 Figure B.3-2 Block Diagram of Stepping Motor Controllerr .......................................................................... 320 Block Diagram of Sound Generator ......................................................................................... 328 Relationship between Tone Signal and Register Value .......................................................... 332 Relationship between Register Value and PWM Pulse ........................................................... 333 Block Diagram of ROM Correction .......................................................................................... 338 System Structure Example ..................................................................................................... 340 ROM Correction Processing Example ..................................................................................... 341 Processing Flow of ROM Correction ....................................................................................... 342 ROM Correction Processing Flow Diagram ............................................................................. 343 Block Diagram of ROM Mirroring Module ................................................................................ 346 Block Diagram of the Entire Flash Memory ............................................................................. 351 Sector Configuration of the 2M/3M-Bit Flash Memory ............................................................. 352 Example of the Flash Memory Write Procedure ...................................................................... 368 Example of the Flash Memory Sector Erase Procedure ......................................................... 371 Example of Serial Write Connection for MB90F591/MB90F594A Internal Vector Modes (User Power Supply Used) ...................................................................................................... 385 Example of Serial Write Connection for MB90F591/MB90F594A Internal Vector Modes (Power Supplied from the Writer) ............................................................................................ 387 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used) ...................................................................................................... 389 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Writer) ............................................................................................ 391 Example of immediate addressing (#imm) .............................................................................. 408 Example of Register Direct Addressing ................................................................................... 409
xv
Figure B.3-3 Figure B.3-4 Figure B.3-5 Figure B.3-6 Figure B.3-7 Figure B.3-8 Figure B.3-9 Figure B.3-10 Figure B.3-11 Figure B.4-1 Figure B.4-2 Figure B.4-3 Figure B.4-4 Figure B.4-5 Figure B.4-6 Figure B.4-7 Figure B.4-8 Figure B.4-9 Figure B.4-10 Figure B.4-11 Figure B.4-12 Figure B.4-13 Figure B.9-1 Figure B.9-2 Figure C-1 Figure C-2 Figure C-3 Figure C-4 Figure C-5 Figure C-6 Figure C-7 Figure C-8 Figure C-9 Figure C-10
Example of Direct Branch Addressing (addr16) ..................................................................... 409 Example of Direct Branch Addressing (addr24) ..................................................................... 409 Example of I/O Direct Addressing (io) .................................................................................... 410 Example of Abbreviated Direct Addressing (dir) ..................................................................... 410 Example of Direct Addressing (addr16) .................................................................................. 410 Example of I/O Direct Bit Addressing (io:bp) .......................................................................... 411 Example of Abbreviated Direct Bit Addressing (dir:bp) ........................................................... 411 Example of Direct Bit addressing (addr16:bp) ........................................................................ 411 Example of Vector Addressing (#vct) ..................................................................................... 412 Example of Register Indirect Addressing (@RWj j = 0 to 3) .................................................. 413 Example of Register Indirect Addressing with Post Increment (@RWj + j = 0 to 3) .............. 413 Example of Register Indirect Addressing with Offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) ........................................................... 414 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3) ............ 414 Example of Program Counter Indirect Addressing with Offset (@PC + disp16) ..................... 415 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7) 415
Example of Program Counter Relative Branch Addressing (rel) ............................................ 416 Configuration of the Register List ........................................................................................... 416 Example of Register List (rlist) ................................................................................................ 416 Example of Accumulator Indirect Addressing (@A) ................................................................ 417 Example of Accumulator Indirect Branch Addressing (@A) ................................................... 417 Example of Indirect Specification Branch Addressing (@ear) ................................................ 418 Example of Indirect Specification Branch Addressing (@eam) .............................................. 418 Structure of Instruction Map .................................................................................................... 438 Correspondence between Actual Instruction Code and Instruction Map ................................ 439 Timing Diagram for Read Access ........................................................................................... 460 Write Data polling Read (WE control) ..................................................................................... 460 Timing Diagram for Write Access (CE Control) ...................................................................... 461 Timing Diagram for Write Access (Chip Erasing/Sector Erasing) ........................................... 461 Timing Diagram for Data Polling ............................................................................................. 462 Timing Diagram for Toggle Bit ................................................................................................ 462 Timing Diagram for Output of RY/BY Signal during Writing/Erasing ...................................... 462 Timing Diagram for Output of RY/BY Signal at Hardware Reset ............................................ 463 Enable Sector Protect/Verify Sector Protect ........................................................................... 463 Temporary Sector Protect Cancellation .................................................................................. 464
xvi
TABLES
Table 1.1-1 Table 1.2-1 Table 1.6-1 Table 1.7-1 Table 2.5-1 Table 2.7-1 Table 2.8-1 Table 2.8-2 Table 2.9-1 Table 3.2-1 Table 3.3-1 Table 3.3-2 Table 3.3-3 Table 3.5-1 Table 3.8-1 Table 3.8-2 Table 5.3-1 Table 5.3-2 Table 6.2-1 Table 6.2-2 Table 6.2-3 Table 6.3-1 Table 6.3-2 Table 7.2-1 Table 7.3-1 Table 7.3-2 Table 7.3-3 Table 9.2-1 Table 10.1-1 Table 10.1-2 Table 12.2-1 Table 12.2-2 Table 12.2-3 Table 12.2-4 Table 14.4-1
Product Overview ....................................................................................................................... 2 MB90590 Features ..................................................................................................................... 3 Pin Functions .............................................................................................................................. 8 Input-output Circuits ................................................................................................................. 12 Default Space ........................................................................................................................... 22 Levels Indicated by the Interrupt Level Mask (ILM) Register ................................................... 30 Register Functions .................................................................................................................... 33 Relationship between Registers ............................................................................................... 33 Bank Select Prefix .................................................................................................................... 35 Interrupt Vectors ....................................................................................................................... 43 Interrupt Level Setting Bits and Interrupt Levels ....................................................................... 44 ICS bits, Channel Numbers, and Descriptor Addresses ........................................................... 46 S Bits and End Conditions ........................................................................................................ 46 Compensation Values for Interrupt Processing Cycle Count ................................................... 52 Execution Time when the Extended EI2OS Continues ............................................................. 62 Data Transfer Compensation Values for Extended EI2OS Execution Time ............................. 62 Reset Causes ........................................................................................................................... 73 Reset Cause Bits ...................................................................................................................... 74 CG Bit Setting ........................................................................................................................... 80 WS Bit Setting .......................................................................................................................... 81 CS Bit Setting ........................................................................................................................... 82 Low-power mode status ........................................................................................................... 83 List of Instructions Used for Transition to Low-power Mode ..................................................... 84 Mode Pins and Modes .............................................................................................................. 95 Mode Setting Bits and Functions .............................................................................................. 96 Bus Mode Setting Bits and Functions ....................................................................................... 96 Sample Recommended Setting of Mode Pins and Mode Data ................................................ 97 Selecting the Time Base Timer Interval .................................................................................. 107 Reset Cause Registers ........................................................................................................... 113 Watch-dog Timer Interval Selection Bit .................................................................................. 113 Clock Sources for CSL Bit Settings ........................................................................................ 145 MOD2, 1, 0 Bit Settings (1) ..................................................................................................... 146 MOD2, 1, 0 Bit Settings (2) ..................................................................................................... 146 OUTE, RELD, and OUTL Settings ......................................................................................... 146 Reload Operation and Pulse Output ....................................................................................... 175 xvii
Table 15.2-1 Table 16.3-1 Table 17.3-1 Table 17.3-2 Table 17.3-3 Table 17.3-4 Table 17.4-1 Table 17.5-1 Table 17.6-1 Table 18.2-1 Table 18.2-2 Table 18.2-3 Table 18.2-4 Table 18.2-5 Table 18.2-6 Table 18.2-7 Table 18.2-8 Table 18.3-1 Table 18.5-1 Table 19.3-1 Table 19.4-1 Table 19.5-1 Table 19.5-2 Table 19.6-1 Table 19.6-2 Table 24.3-1 Table 24.5-1 Table 24.6-1 Table 24.6-2 Table 24.6-3 Table 24.6-4 Table 24.6-5 Table 24.6-6 Table 24.6-7 Table 24.6-8 Table 24.6-9
Interrupt Request Detection Factor for LBx and LAx Pins ..................................................... 187 Operation Mode Setting ......................................................................................................... 198 UART Operation Modes ........................................................................................................ 221 UIDR State after Receive Completion ................................................................................... 223 Clock Input Selection ............................................................................................................. 226 Clock Input Selection ............................................................................................................. 226 UART0 Operating Modes ...................................................................................................... 228 Baud Rate .............................................................................................................................. 230 Baud Rate and Reload Value ................................................................................................ 232 Setting the Serial Mode Selection Bit .................................................................................... 246 Setting the Transfer Direction Selection Bit ........................................................................... 246 Setting the Serial Output Enable Bit ...................................................................................... 247 Setting the Shift Clock Output Enable Bit .............................................................................. 247 Setting the Serial Shift Clock Mode ....................................................................................... 247 Setting the Interrupt Request Enable Bit ............................................................................... 248 Setting the Transfer Status Bit ............................................................................................... 248 Setting the Stop Bit ................................................................................................................ 249 Machine Clock Division Ratio ................................................................................................ 251 Setting the NEG Bit ................................................................................................................ 259 List of Overall Control Registers ............................................................................................ 264 List of Message Buffers (ID Registers) .................................................................................. 266 List of Message Buffers (DLC Registers and Data Registers) ............................................... 269 List of Message Buffers (Data Registers) ............................................................................. 271 Correspondence between NS1 and NS0 and Node Status ................................................... 275 Selection of Acceptance Mask ............................................................................................... 295 Flash Memory Control Signals ............................................................................................... 353 Command Sequence Table ................................................................................................... 357 Bit Assignments of Hardware Sequence Flags ...................................................................... 358 Hardware Sequence Flag Functions .................................................................................... 359
Data Polling Flag State Transitions (State Change for Normal Operation) ........................... 360 Data Polling Flag State Transitions (State Change for Abnormal Operation) ........................ 360 Toggle Bit Flag State Transitions (State Change for Normal Operation) ............................... 362 Toggle Bit Flag State Transitions (State Change for Abnormal Operation) ........................... 362 Timing Limit Exceeded Flag State Transitions (State Change for Normal Operation) .......... 363 Timing Limit Exceeded Bit Flag State Transitions (State Change for Abnormal Operation) . 363 Sector Erase Timer Flag State Transitions (State Change for Normal Operation) ................ 364
Table 24.6-10 Sector Erase Timer Flag State Transitions (State Change for Abnormal Operation) ............ 364 Table 25.1-1 Pins Used for Fujitsu Standard Serial Onboard Writing ......................................................... 382
xviii
Table 25.1-2 Table A-1 Table A-2 Table B.2-1 Table B.3-1 Table B.3-2 Table B.5-1 Table B.5-2 Table B.5-3 Table B.6-1 Table B.7-1 Table B.7-2 Table B.8-1 Table B.8-2 Table B.8-3 Table B.8-4 Table B.8-5 Table B.8-6 Table B.8-7 Table B.8-8 Table B.8-9 Table B.8-10 Table B.8-11 Table B.8-12 Table B.8-13 Table B.8-14 Table B.8-15 Table B.8-16 Table B.8-17 Table B.9-1 Table B.9-2 Table B.9-3 Table B.9-4 Table B.9-5 Table B.9-6 Table B.9-7 Table B.9-8
AF200 Flash Microcomputer Programmer System Configuration (Manufactured by Yokogawa Digital Computer Ltd.) ........................................................................................... 383 I/O Map ................................................................................................................................... 394 I/O Map (19XX Address) ........................................................................................................ 399 Effective Address Field ........................................................................................................... 407 Direct Addressing Registers ................................................................................................... 408 CALLV Vector List .................................................................................................................. 412 Execution Cycle Counts in Each Addressing Mode ............................................................... 419 Cycle Count Correction Values for Counting Execution Cycles ............................................. 420 Cycle Count Correction Values for Counting Instruction Fetch Cycles .................................. 420 Effective Address Field ........................................................................................................... 422 Description of Items in the Instruction List .............................................................................. 424 Explanation on Symbols in the Instruction List ....................................................................... 425 41 Transfer Instructions (byte) ................................................................................................ 427 38 Transfer Instructions (byte) ................................................................................................ 428 42 Addition/subtraction Instructions (byte, word, long word) .................................................. 429 12 Increment/decrement Instructions (byte, word, long word) ................................................ 429 11 Compare Instructions (byte, word, long word) ................................................................... 430 11 unsigned multiplication/division instructions (word, long word) ......................................... 430 39 Logic 1 Instructions (byte, word) ........................................................................................ 431 Six Logic 2 Instructions (long word) ........................................................................................ 432 Six Sign Inversion Instructions (byte, word) ........................................................................... 432 One Normalization Instruction (long word) ............................................................................. 432 18 Shift Instructions (byte, word, long word) .......................................................................... 432 31 Branch 1 Instructions ........................................................................................................ 433 19 Branch 2 Instructions ........................................................................................................ 434 31 28 Other Control Instructions (byte, word, long word) ...................................................... 435 21 Bit Operand Instructions ................................................................................................... 435 Six Accumulator Operation Instructions (byte, word) ............................................................ 436 Ten String Instructions ........................................................................................................... 436 Example of an Instruction Code ............................................................................................. 439 Basic Page Map ...................................................................................................................... 440 Bit Operation Instruction Map (first byte = 6CH) ...................................................................... 441 Character String Operation Instruction Map (first byte = 6EH) ................................................ 442 2-byte Instruction Map (first byte = 6FH) ................................................................................. 443 ea Instruction 1 (first byte = 70H) ............................................................................................ 444 ea Instruction 2 (first byte = 71H) ............................................................................................ 445 ea Instruction 3 (first byte = 72H) ............................................................................................ 446
xix
Table B.9-9 Table B.9-10 Table B.9-11 Table B.9-12 Table B.9-13 Table B.9-14 Table B.9-15 Table B.9-16 Table B.9-17 Table B.9-18 Table B.9-19 Table B.9-20 Table B.9-21 Table D-1 Table D-2
ea Instruction 4 (first byte = 73H) ........................................................................................... 447 ea Instruction 5 (first byte = 74H) ........................................................................................... 448 ea Instruction 6 (first byte = 75H) ........................................................................................... 449 ea Instruction 7 (first byte = 76H) ........................................................................................... 450 ea Instruction 8 (first byte = 77H) ........................................................................................... 451 ea Instruction 9 (first byte = 78H) ........................................................................................... 452 MOVEA RWi, ea Instruction (first byte = 79H) ........................................................................ 453 MOV Ri, ea Instruction (first byte = 7AH) ................................................................................ 454 MOVW RWi, ea Instruction (first byte = 7BH) ......................................................................... 455 MOV ea, Ri Instruction (first byte = 7CH) ............................................................................... 456 MOVW ea, Rwi Instruction (first byte = 7DH) ......................................................................... 457 XCH Ri, ea Instruction (first byte = 7EH) ................................................................................ 458 XCHW RWi, ea Instruction (first byte = 7FH) .......................................................................... 459 MB90590 Interrupt Vectors .................................................................................................... 465 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers .................................... 467
xx
CHAPTER 1
OVERVIEW
The MB90590 Series is a family menber of the F2MC-16LX micro controllers. 1.1 Product Overview 1.2 Features 1.3 Block Diagram 1.4 Pin Assignment 1.5 Package Dimensions 1.6 Pin Functions 1.7 Circuit 1.8 Handling the Device
1
CHAPTER 1 OVERVIEW
1.1
Product Overview
Table 1.1-1 provides a quick outlook of the MB90590 Series.
s Product Overview
Table 1.1-1 Product Overview Features Product type CPU System clock ROM/Flash memory External MB90V590A Evaluation sample MB90F594A/F591 Flash version F2MC-16LX CPU On-chip PLL clock multiplier (x1, x2, x3, x4, 1/2 when PLL stop) Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL x4) Boot-block Flash memory 256K/384K bytes with Hard-wired reset vector 8Kbytes 0.5 m CMOS with on-chip voltage regulator for internal power supply Mask ROM 256K/384K bytes MB90594/591 Mask ROM version
RAM Technology
6K/8K bytes 0.5 m CMOS + Flash memory with on-chip voltage regulator for internal power supply and on-chip charge pump for programming voltage 0.5 m CMOS with on-chip voltage regulator for internal power supply
Package
PGA-256
QFP100
2
1.2 Features
1.2
Features
Table 1.2-1 lists the features of the MB90590 series.
s Features
Table 1.2-1 MB90590 Features Function UART (3 channels) Feature Full duplex double buffer Supports asynchronous/synchronous(with start/stop bit) transfer Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000bps (asynchronous) 500K/1M/2Mbps (synchronous) at System clock = 16MHz Transfer can be started from MSB or LSB Supports internal clock synchronized transfer and external clock synchronized transfer Supports positive-edge and negative-edge clock synchronization Baud rate : 31.25K/62.5K/125K/500K/1Mbps at System clock = 16MHz 10 or 8-bit resolution 8 input channels Conversion time : 26.3us (per one channel) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function Directly operates with the oscillation clock Facility to correct oscillation deviation Read/Write accessible Second/Minute/Hour registers Signals interrupts Signals an interrupt when overflow Supports Timer Clear when a match with Output Compare(Channel 0) Operation clock frequency : fsys/22, fsys/24,fsys/26, fsys/28(fsys = System clock frequency) Signals an interrupt when a match with 16-bit IO Timer Six 16-bit compare registers A pair of compare registers can be used to generate an output signal Rising edge, falling edge or rising & falling edge sensitive Six 16-bit Capture registers Signals an interrupt upon external event
Serial IO
A/D Converter 16-bit Reload Timer (2 channels) Watch Timer
16-bit IO Timer
16-bit Output Compare (6 channels) 16-bit Input Capture (6 channels)
3
CHAPTER 1 OVERVIEW Table 1.2-1 MB90590 Features (Continued) Function 8/16-bit Programmable Pulse Generator (6 channels) Feature Supports 8-bit and 16-bit operation modes Twelve 8-bit reload counters Twelve 8-bit reload registers for L pulse width Twelve 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter 6 output pins Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128us@fosc=4MHz (fsys = System clock frequency, fosc = Oscillation clock frequency) Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID's Supports multiple messages Flexible configuration of acceptance filtering : Full bit compare / Full bit mask / Two partial bit masks Supports up to 1Mbps Four high current outputs for each channel Synchronized two 8-bit PWM*s for each channel Succeeds to MB89940 design resource Can be programmed edge sensitive or level sensitive
CAN Interface (2 channels)
Stepping Motor Controller (4 channels) External Interrupt (8 channels) Sound Generator
8-bit PWM signal is mixed with tone frequency from 8-bit reload counter PWM frequency : 62.5K, 31.2K, 15.6K, 7.8KHz at System clock = 16MHz Tone frequency : PWM frequency / 2 / (reload value + 1) Virtually all external pins can be used as general purpose IO All push-pull outputs and schmitt trigger inputs Bit-wise programmable as input/output or peripheral signal Supports automatic programming, Embedded AlgorithmTM *1 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Flash Writer from Minato Electronics Inc. Boot block configuration Erase can be performed on each block
IO Ports
Flash Memory
*1: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
4
1.3 Block Diagram
1.3
Block Diagram
Figure 1.3-1 shows a block diagram of the MB90590 series.
s Block Diagram
Figure 1.3-1 Block Diagram
X0,X1 RSTX HSTX Clock Controller 16LX CPU
RAM 6K/8K
IO Timer Input Capture 6ch Output Compare 6ch
IN[5:0]
ROM/Flash 256K/384K
OUT[5:0]
Prescaler x3
SOT[2:0] SCK[2:0] SIN[2:0] UART 3ch
8/16-bit PPG 6ch
PPG[5:0]
Prescaler FMC-16 Bus CAN 2ch RX[1:0] TX[1:0]
SOT3 SCK3 SIN3 Serial I/O
PWM1M[3:0] PWM1P[3:0]
AVCC AVSS AN[7:0] AVRH AVRL ADTG 10-bit ADC 8ch
SMC 4ch
PWM2M[3:0] PWM2P[3:0] DVCC[1:0] DVSS[2:0]
External Interrupt TIN TOT/WOT 16-bit Reload Timer 2ch Sound Generator Watch Timer
INT[7:0]
SGO SGA
5
6
Vss X0 X1 Vcc P00/IN0 P01/IN1 P02/IN2 P03/IN3 P04/IN4 P05/IN5 P06/OUT0 P07/OUT1 P10/OUT2 P11/OUT3 P12/OUT4 P13/OUT5 P14/RX1 P15/TX1 80
P95/INT3 P94/INT2 P93/INT1
RST
1.4
s Pin Assignment
CHAPTER 1 OVERVIEW
P16/SGO
Pin Assignment
P17/SGA 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
QFP-100
Figure 1.4-1 Pin Assignment
Package code (mold) FPT-100P-M06
P92/INT0 P91/RX0 P90/TX0 DVSS P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 DVCC P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 DVCC P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 DVSS
HST
Figure 1.4-1 shows the pin assignments for the MB90590 series.
P20 P21 P22 P23 P24/INT4 P25/INT5 P26/INT6 P27/INT7 P30 P31 Vss P32 P33 P34/SOT0 P35/SCK0 P36/SIN0 P37/SIN1 P40/SCK1 P41/SOT1 P42/SOT2 P43/SCK2 P44/SIN2 Vcc P45/SCIN3 P46/SCK3 P47/SOT3 C P50/PPG0 P51/PPG1 P52/PPG2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MD2
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 MD1 MD0 P57/TOT/WOT P56/TIN P67/AN7 P66/AN6 P65/AN5 P64/AN4 Vss P63/AN3 P62/AN2 P61/AN1 P60/AN0 AVss AVR- AVR+ AVcc P55/PPG5/ADTG P54/PPG4 P53/PPG3
1.5 Package Dimensions
1.5
Package Dimensions
Figure 1.5-1 shows the package dimensions of the MB90590 series.
s Package Dimensions
Figure 1.5-1 Package Dimensions
FPT-100P-M06
EIAJ Code: QFP100-P-1420-4
Lead pitch
Plastic QFP, 100 pins
0.65mm 14 x 20mm Gull wing Plastic mold 0.80mm
Package width x package length Lead configuration Sealing Flat portion length
(FPT-100P-M06)
Plastic QFP, 100 pins
(FPT-100P-M06)
23.90 0.40(.941 .016) 3.35(.132)MAX (Mounting height)
80 81
20.00 0.20(.787 .008)
51 50
0.05(.002)MIN
14.00 0.20 (.551 .008)
17.90 0.40 (.705 .016)
12.35(.486) REF
16.30 0.40 (.642 .016)
INDEX 100 "A" LEAD No. 1 30 31
0.65(.0256)TYP
0.30 0.10 (.012 .004)
0.13(.005)
M
0.15 0.05(.006 .002)
Details of "A" part 0.25(.010) "B" Details of "B" part
0.10(.004) 18.85(.742)REF 22.30 0.40(.878 .016)
0.30(.012) 0.18(.007)MAX 0.53(.021)MAX
0
10
0.80 0.20 (.031 .008)
(c) 1992 FUJITSU LIMITED F100008-3C-1
Units: mm (inches)
7
CHAPTER 1 OVERVIEW
1.6
Pin Functions
Table 1.6-1 describes the pin functions of the MB90590 series.
s Pin Functions
Table 1.6-1 Pin Functions No. 82 83 77 52 85 to 90 IN0 to IN5 P06 to P07 P10 to P13 91 to 96 OUT0 to OUT5 P14 97 RX1 P15 98 TX1 D D RX input for CAN Interface 1 General purpose IO TX output for CAN Interface 1. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". General purpose IO D SGO output for the Sound Generator. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". General purpose IO D SGA output for the Sound Generator. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". General purpose IO General purpose IO D External interrupt input for INT4 to INT7 These pin functions are not supported by MB90V590 D Pin name X0 A X1 RST HST P00 to P05 D Inputs for the Input Captures General purpose IO Outputs for the Output Compares. To enable the signal outputs, the corresponding bits of the Port Direction registers should be set to "1". General purpose IO B C Oscillation output Reset input Hardware standby input General purpose IO Circuit type Oscillation input Function
P16 99 SGO
P17 100 SGA
1 to 4
P20 to P23 P24 to P27
D
5 to 8
INT4 to INT7
8
1.6 Pin Functions Table 1.6-1 Pin Functions (Continued) No. 9 to 10 12 to 13 Pin name P30 to P31 P32 to P33 P34 14 SOT0 D Circuit type D D General purpose IO General purpose IO General purpose IO SOT output for UART 0. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". General purpose IO D SCK input/output for UART 0. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". General purpose IO D SIN0 P37 17 SIN1 P40 18 SCK1 P41 19 SOT1 P42 20 SOT2 P43 21 SCK2 P44 22 SIN2 P45 24 SIN3 P46 25 SCK3 P47 26 SOT3 P50 to P55 28 to 33 PPG0 to PPG5, ADTG D D SOT output for the Serial IO General purpose IO Outputs for the Programmable Pulse Generators. Pin number 33 is also shared with ADTG input for the external trigger of the A/D Converter. D SCK input/output for the Serial IO General purpose IO D SIN input for the Serial IO General purpose IO D SIN input for UART 2 General purpose IO D SCK input/output for UART 2 General purpose IO D SOT output for UART 2 General purpose IO D SOT output for UART 1 General purpose IO D SCK input/output for UART 1 General purpose IO D SIN input for UART 1 General purpose IO SIN input for UART 0 General purpose IO Function
P35 15 SCK0
P36 16
9
CHAPTER 1 OVERVIEW Table 1.6-1 Pin Functions (Continued) No. 38 to 41 AN0 to AN3 P64 to P67 43 to 46 AN4 to AN7 P56 47 TIN P57 48 TOT/WOT D D TIN input for the 16-bit Reload Timers General purpose IO TOT output for the 16-bit Reload Timers and WOT output for the Watch Timer. Only one of three output enable flags in these pheripheral blocks can be set at a time. Otherwise the output signal has no meaning. General purpose IO F Output for Stepping Motor Controller channel 0. E Inputs for the A/D Converter General purpose IO Pin name P60 to P63 E Inputs for the A/D Converter General purpose IO Circuit type General purpose IO Function
P70 to P73 54 to 57 PWM1P0 PWM1M0 PWM2P0 PWM2M0 P74 to P77 59 to 62 PWM1P1 PWM1M1 PWM2P1 PWM2M1 P80 to P83 64 to 67 PWM1P2 PWM1M2 PWM2P2 PWM2M2 P84 to P87 69 to 72 PWM1P3 PWM1M3 PWM2P3 PWM2M3 P90 74 TX0 P91 75 RX0 P92 76 INT0 D D D F F F
General purpose IO Output for Stepping Motor Controller channel 1.
General purpose IO Output for Stepping Motor Controller channel 2.
F, GGeneral purpose IO Output for Stepping Motor Controller channel 3.
General purpose IO TX output for CAN Interface 0 General purpose IO RX input for CAN Interface 0 General purpose IO External interrupt input for INT0
10
1.6 Pin Functions Table 1.6-1 Pin Functions (Continued) No. 78 INT1 P94 79 INT2 P95 80 INT3 58 68 53 63 73 34 37 35 36 49 50 51 27 23 84 11 42 81 DVCC DVSS D External interrupt input for INT3 Dedicated power supply pins for the high current output buffers (Pin No. 54 to 72) Dedicated ground pins for the high current output buffers (Pin No. 54 to 72) Dedicated power supply pin for the A/D Converter Dedicated ground pin for the A/D Converter Upper referance voltage input for the A/D Converter Lower reference voltage input for the A/D Converter C H Test mode inputs. These pins should be connected to VCC Test mode input. This pin should be connected to VSS External capacitor pin. A capacitor of 0.1F should be connected to this pin and VSS. Power supply pins Ground pins D External interrupt input for INT2 General purpose IO Pin name P93 D External interrupt input for INT1 General purpose IO Circuit type General purpose IO Function
AVCC AVSS AVR+ AVRMD0 MD1 MD2 C VCC VSS
11
CHAPTER 1 OVERVIEW
1.7
Input-Output Circuits
Table 1.7-1 lists the input-output circuits.
s Input-output Circuits
Table 1.7-1 Input-output Circuits Class A
X1
Circuit *
Remarks 2Oscillation feedback resistor: 1 Mohm approx.
X0
Standby control signal
B
*
Hysteresis input with pull-up Resistor: 50 Kohm approx.
HYS
C
HYS
*
Hysteresis input
12
1.7 Input-Output Circuits Table 1.7-1 Input-output Circuits (Continued) Class D Circuit * * Remarks CMOS output Hysterisis input
HYS
E
* * *
CMOS output Hysterisis input Analog input
Analog input
HYS
F
* *
CMOS high current output Hysterisis input
High current
HYS
13
CHAPTER 1 OVERVIEW Table 1.7-1 Input-output Circuits (Continued) Class G Circuit * * * Remarks CMOS high current output Hysterisis input Analog input
High current
Analog input HYS
H * Hysteresis input with pull-down Resistor: 50 Kohm approx. Flash version does not have pull-down register.
HYS
14
1.8 Handling the Device
1.8
Handling the Device
Special care is required for the following when handling the device: * Preventing latch-up * Handling unused input pins * Using external clock * Power supply pins (Vcc/Vss) * Pull-up/down resistors
s Handling the Device
r Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions: * * * A voltage higher than Vcc or lower than Vss is applied to an input or output pin. A voltage higher than the rated voltage is applied between Vcc and Vss. The AVcc power supply is applied before the Vcc voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device. r Handling unused input pins Do not leave unused input pins open, as doing so may cause misoperation of the device. Use a pull-up or pull-down resistor. r Using external clock To use external clock, drive the X0 and X1 pins in reverse phase. Figure 1.8-1 is a diagram of how to use external clock. Figure 1.8-1 Using External Clock
MB90590 Series X0 X1
r Power supply pins (Vcc/Vss) Ensure that all Vcc-level power supply pins are at the same potential. In addition, ensure the same for all Vss-level power supply pins. (See the figure 1.8-2.) If there are more than one Vcc or Vss system, the device may operate incorrectly even within the guaranteed operating range.
15
CHAPTER 1 OVERVIEW Figure 1.8-2 Power Supply Pins (Vcc/Vss)
Vcc Vss
Vcc Vss Vcc
Vss
MB90590 Series
Vcc Vss
Vss
Vcc
r Pull-up/down resistors The MB90590 Series does not support internal pull-up/down resistors. Use external components where needed.
16
CHAPTER 2
CPU
This chapter explains the memory space of the MB90590. 2.1 Outline of CPU 2.2 Memory Space 2.3 Memory Space Map 2.4 Linear Addressing 2.5 Bank Addressing Types 2.6 Multi-byte Data in Memory Space 2.7 Registers 2.8 Register Bank 2.9 Prefix Codes 2.10 Interrupt Disable Instructions
17
CHAPTER 2 CPU
2.1
Outline of CPU
The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require highspeed real-time processing, such as home-use or vehicle-mounted electronic appliances. The F2MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing.
s
Outline of CPU
In addition to 16-bit data, the F2MC-16LX CPU core can process 32-bit data by using an internal 32-bit accumulator. (32-bit data can be processed with some instructions.) Up to 16 Mbytes of memory space (expandable) can be used, which can be accessed by either the linear pointer or bank method. The instruction system, based on the F2MC-8 A-T architecture, has been reinforced by adding instructions compatible with high-level languages, expanding addressing modes, reinforcing multiplication and division instructions, and enhancing bit processing. The features of the F2MC-16LX CPU are explained below. r Minimum instruction execution time: 62.5 ns (at 4-MHz oscillation, 4 times clock multiplication) r Maximum memory space: 16 Mbytes, accessed in linear or bank mode r Instruction set optimized for controller applications * * * Rich data types: Bit, byte, word, long word Extended addressing modes: 23 types High-precision operation (32-bit length) based on 32-bit accumulator
r Powerful interrupt functions Eight priority levels (programmable) r CPU-independent automatic transfer Up to 16 channels of the extended intelligent I/O service r Instruction set compatible with high-level language (C)/multitasking System stack pointer/instruction set symmetry/barrel-shift instructions r Improved execution speed: 4-byte queue
18
2.2 Memory Space
2.2
Memory Space
An F2MC-16LX CPU has a 16-Mbyte memory space. All data program input and output managed by the F2MC-16LX CPU are located in this 16-Mbyte memory space. The CPU accesses the resources by indicating their addresses using a 24-bit address bus.
s Outline of CPU Memory Space Figure 2.2-1 shows a sample relationship between the F2MC-16LX system and memory map. Figure 2.2-1 Sample Relationship between F2MC-16LX System and Memory Map
Program F2MC-16LX CPU Data Interrupt Peripheral circuits [Device] Generalpurpose ports FFFFFF H FF8000H 810000H Data area 800000H 0000C0H 0000B0 H 000020H 000000H Interrupt controller Peripheral circuits General-purpose ports Program area
s Address Generation Types The F2MC-16LX has the following two addressing: r Linear addressing An entire 24-bit address is specified by an instruction. r Bank addressing The eight high-order bits of an address are specified by an appropriate bank register, and the remaining 16 low-order bits are specified by an instruction.
19
CHAPTER 2 CPU
2.3
Memory Space Map
The memory space of the MB90590 Series is shown in Figure 2.3-1.
s Memory Space Map The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00. The image between FF4000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH is visible only in bank FF. Figure 2.3-1 Memory Space Map
MB90V590A
FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H ROM (F9 bank) F90000H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank)
MB90F594A/MB90594
FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank)
MB90F591/MB90591
FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH ROM (F9 bank) ROM (FB bank) ROM (FA bank) ROM (FF bank) ROM (FE bank) ROM (FD bank)
00FFFFH 004000H 0028FFH 002100H 0020FFH 001FFFH 001900H 0018FFH
ROM (Image of FF bank)
00FFFFH 004000H
ROM (Image of FF bank)
00FFFFH 004000H 0028FFH
ROM (Image of FF bank)
RAM 2K 002100H 0020FFH 001FFFH Peripheral 001900H 0018FFH Peripheral 001FFFH 001900H 0018FFH
RAM 2K
Peripheral
RAM 6K 000100H 0000BFH 000000H Peripheral 000100H 0000BFH 000000H
RAM 6K 000100H Peripheral 0000BFH 000000H
RAM 6K
Peripheral
20
2.4 Linear Addressing
2.4
Linear Addressing
There are two types of linear addressing: * 24-bit operand specification: Directly specifies a 24-bit address using operands. * 32-bit register indirect specification: Indirectly specifies the 24 low-order bits of a 32-bit general-purpose register value as the address.
s 24-bit Operand Specification Figure 2.4-1 shows an example of 24-bit operand specification. Figure 2.4-2 shows an example of 32-bit register indirect specification. Figure 2.4-1 Example of Linear Method (24-bit Register Operand Specification)
JMPP 123456 H Old program counter + program bank 17 452D 17452D H JMPP 123456 H
123456 H New program counter + program bank 12 3456
Next instruction
Figure 2.4-2 Example of Linear Method (32-bit Register Indirect Specification)
MOV A, @RL1+7 090700 H
Old AL
XXXX
3A
+7
RL1 (The high-order eight bits are ignored.)
240906F9
New AL
003A
21
CHAPTER 2 CPU
2.5
Bank Addressing Types
In the bank method, the 16-Mbyte space is divided into 256 64-Kbyte banks. The following five bank registers are used to specify the banks corresponding to each space: * Program bank register (PCB) * Data bank register (DTB) * User stack bank register (USB) * System stack bank register (SSB) * Additional bank register (ADB)
s Bank Addressing Types
r Program bank register (PCB) The 64-Kbyte bank specified by the PCB is called a program (PC) space. The PC space contains instruction codes, vector tables, and immediate value data, for example. r Data bank register (DTB) The 64-Kbyte bank specified by the DTB is called a data (DT) space. The DT space contains readable/writable data, and control/data registers for internal and external resources. r User stack bank register (USB)/system stack bank register (SSB) The 64-Kbyte bank specified by the USP or SSP is called a stack (SP) space. The SP space is accessed when a stack access occurs during a push/pop instruction or interrupt register saving. The S flag in the condition code register determines the stack space to be accessed. r Additional bank register (ADB) The 64-Kbyte bank specified by the ADB is called an additional (AD) space. The AD space, for example, contains data that cannot fit into the DT space. Table 2.5-1 lists the default spaces used in each addressing mode, which are pre-determined to improve instruction coding efficiency. To use a non-default space for an addressing mode, specify a prefix code corresponding to a bank before the instruction. This enables access to the bank space corresponding to the specified prefix code. After reset, the DTB, USB, SSB, and ADB are initialized to 00H. The PCB is initialized to a value specified by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank 00H (000000H to 00FFFFH), and the PC space is allocated in the bank specified by the reset vector. Table 2.5-1 Default Space Default space Program space Data space Addressing mode PC indirect, program access, branch Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir
22
2.5 Bank Addressing Types Table 2.5-1 Default Space (Continued) Default space Stack space Additional space Addressing mode Addressing mode using PUSHW, POPW, @RW3, or @RW7 Addressing mode using @RW2 or @RW6
Figure 2.5-1 is an example of a memory space divided into register banks. Figure 2.5-1 Physical Addresses of Each Space
FFFFFF H FF0000 H B3FFFF H Additional space B30000 H Physical address 92FFFF H 920000 H 68FFFF H 680000 H 4BFFFF H System stack space 4B0000 H 000000 H 4B H : SSB (System stack bank register) Data space 68 H : DTB (Data bank register) User stack space 92 H : USB (User stack bank register) B3 H : ADB (Additional bank register) Program space FF H : PCB (Program bank register)
23
CHAPTER 2 CPU
2.6
Multi-byte Data in Memory Space
Data is written to memory from the low-order addresses. Therefore, for a 32-bit data item, the low-order 16 bits are transferred before the high-order 16 bits. If a reset signal is input immediately after the low-order bits are written, the high-order bits might not be written.
s Multi-byte Data Allocation in Memory Space Figure 2.6-1 is a diagram of multi-byte data configuration in memory. The low-order eight bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc. Figure 2.6-1 Sample Allocation of Multi-byte Data in Memory
MSB H 01010101 11001100 11111111 LSB 00010100
01010101 11001100 11111111 Address n L 00010100
s Accessing Multi-byte Data Fundamentally, accesses are made within a bank. For an instruction accessing a multi-byte data item, address FFFFH is followed by address 0000H of the same bank. Figure 2.6-2 is an example of an instruction accessing multi-byte data. Figure 2.6-2 Execution of MOVW A, 080FFFFH
H AL before execution 80FFFF H 01H * * * 800000 H 23 H AL after execution 23 H 01H ?? ??
L
24
2.7 Registers
2.7
Registers
The F2MC-16LX registers are largely classified into two types: special registers in the CPU and general-purpose registers in memory. The special registers are dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture. The general-purpose registers share the CPU address space with RAM. The general-purpose registers are the same as the special registers in that they can be accessed without using an address. The applications of the general-purpose registers can be specified by the user however, as is ordinary memory space.
s Special Registers The F2MC-16LX CPU core has the following 13 special registers: * * * * * * * * * * * Accumulator (A=AH:AL): Two 16-bit accumulators (Can be used as a single 32-bit accumulator.) User stack pointer (USP): 16-bit pointer indicating the user stack area System stack pointer (SSP): 16-bit pointer indicating the system stack area Processor status (PS): 16-bit register indicating the system status Program counter (PC): 16-bit register holding the address of the program Program bank register (PCB): 8-bit register indicating the PC space Data bank register (DTB): 8-bit register indicating the DT space User stack bank register (USB): 8-bit register indicating the user stack space System stack bank register (SSB): 8-bit register indicating the system stack space Additional bank register (ADB): 8-bit register indicating the AD space Direct page register (DPR): 8-bit register indicating a direct page
Figure 2.7-1 is a diagram of the special registers.
25
CHAPTER 2 CPU Figure 2.7-1 Special Registers
AH AL USP SSP PS PC DPR PCB DTB USB SSB ADB 8 bit 16 bit 32 bit Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register
s General-purpose Registers The F2MC-16LX general-purpose registers are located from addresses 000180H to 00037FH (maximum configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses are currently being used as a register bank. Each bank has the following three types of registers. These registers are mutually dependent as described in Figure 2.7-2. * * * R0 to R7: 8-bit general-purpose register RW0 to RW7: 16-bit general-purpose register RL0 to RL3: 32-bit general-purpose register Figure 2.7-2 General-purpose Registers
MSB 16 bit 000180 H + RP*10 H First address of general-purpose register Low-order RW0 RL0 RW1 RW2 RW3 R1 R3 R5 R7 High-order R0 R2 R4 R6 RW4 RL2 RW5 RW6 RL3 RW7 RL1 LSB
The relationship between the high-order and low-order bytes of a byte or word register is expressed as follows: RW (i+4) = R (i*2+1)*256+R (i*2) [i=0 to 3] The relationship between the high-order and low-order bytes of Rli and RW can be expressed as follows: RL (i) = RW (i*2+1)*65536+RW (i*2) [i=0 to 3] 26
2.7 Registers
2.7.1
Accumulator (A)
The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH and AL), and is used as a temporary storage for operation results and transfer data.
s Accumulator (A) The A register consists of two 16-bit arithmetic operation registers (AH and AL). The A register is used as a temporary storage for operation results and transfer data. During 32-bit data processing, AH and AL are used together. Only AL is used for word processing in 16-bit data processing mode or for byte processing in 8-bit data processing mode (see Figures 2.7-3 and 2.7-4). The data stored in the A register can be operated upon with the data in memory or registers (Ri, Rwi, or Rli). In the same manner as with the F2MC-8L, when a word or shorter data item is transferred to AL, the previous data item in AL is automatically sent to AH (data preservation function). The data preservation function and operation between AL and AH help improve processing efficiency. When a byte or shorter data item is transferred to AL, the data is sign-extended or zeroextended and stored as a 16-bit data item in AL. The data in AL can be handled either as word or byte long. When a byte-processing arithmetic operation instruction is executed on AL, the high-order eight bits of AL before operation are ignored. The high-order eight bits of the operation result all become zeroes. The A register is not initialized by a reset. The A register holds an undefined value immediately after a reset. Figure 2.7-3 32-bit Data Transfer
MO VL A,@R W1+6 Old A XXXX H XXXX H DTB New A 8F74 H AH 2B52 H AL A6 H A61540 H A6153E H +6 RW1 15 H 38 H MSB 8F H 2B H LSB 74 H 52 H
Figure 2.7-4 AL-AH Transfer
MO VW A,@R W1+6 Old A XXXX H 1234 H DTB New A 1234 H 1234 H A6 H A61540 H A6153E H +6 RW1 15 H 38 H MSB 8F H 2B H 74 H 52 H LSB
27
CHAPTER 2 CPU
2.7.2
User Stack Pointer (USP) and System Stack Pointer (SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data when a push/pop instruction or subroutine is executed.
s User Stack Pointer (USP) and System Stack Pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data in the event of a push/pop instruction or subroutine execution. The USP and SSP registers are used by stack instructions. The USP register is enabled when the S flag in the processor status register is '0,' and the SSP register is enabled when the S flag is '1' (see Figure 2.7-5). Since the S flag is set when an interrupt is accepted, register values are always saved in the memory area indicated by SSP during interrupt processing. SSP is used for stack processing in an interrupt routine, while USP is used for stack processing outside an interrupt routine. If the stack space is not divided, use only the SSP. During stack processing, the high-order eight bits of an address are indicated by SSB (for SSP) or USB (for USP). USP and SSP are not initialized by a reset. Instead, they hold undefined values. Figure 2.7-5 Stack Manipulation Instruction and Stack Pointer
Example 1 PUSHW A when the S flag is '0' Before execution AL S flag A624 H 0 USB SSB C6 H 56 H USP SSP F328 H 1234 H MSB C6F326 H XX LSB XX
After execution
AL
A624 H 0
USB SSB
C6 H 56 H
USP SSP
F326 H 1234 H
User stack is used because the S flag is '0.' C6F326 H A6 H 24 H
Example 2 PUSHW A when the S flag is '1' AL A624 H 1 USB SSB C6 H 56 H USP SSP F328 H 1234 H 561232 H XX XX
AL
A624 H 1
USB SSB
C6 H 56 H
USP SSP
F328 H 1232 H
561232 H
A6 H
24 H
System stack is used because the S flag is '1.'
Note: Specify an even-numbered address in the stack pointer whenever possible.
28
2.7 Registers
2.7.3
Processor Status (PS)
The PS register consists of the bits controlling the CPU Operation and the bits indicating the CPU status.
s Processor Status (PS) As shown in Figure 2.7-6, the high-order byte of the PS register consists of a register bank pointer (RP) and an interrupt level mask register (ILM). The RP indicates the start address of a register bank. The low-order byte of the PS register is a condition code register (CCR), containing the flags to be set or reset depending on the results of instruction execution or interruptoccurrences. Figure 2.7-6 Processor Status (PS) Structure
15 PS ILM 13 12 RP 87 CCR 0
s Condition Code Register (CCR) Figure 2.7-7 is a diagram of condition code register configuration. Figure 2.7-7 Condition Code Register (CCR) Configuration
7 Initial value 6 I 0 5 S 1 4 T * 3 N * * 2 Z * 1 V * 0 C : CCR *: Undefined
r I: Interrupt enable flag: Interrupts other than software interrupts are enabled when the I flag is 1 and are masked when the I flag is 0. The I flag is cleared by a reset. r S: Stack flag: When the S flag is 0, USP is enabled as the stack manipulation pointer. When the S flag is 1, SSP is enabled as the stack manipulation pointer. The S flag is set by an interrupt reception or a reset. r T: Sticky bit flag: 1 is set in the T flag when there is at least one '1' in the data shifted out from the carry after execution of a logical right/arithmetic right shift instruction. Otherwise, 0 is set in the T flag. In addition, '0' is set in the T flag when the shift amount is zero. r N: Negative flag: The N flag is set when the MSB of the operation result is '1,' and is otherwise cleared. r Z: Zero flag: The Z flag is set when the operation result is all zeroes, and is otherwise cleared.
29
CHAPTER 2 CPU r V: Overflow flag: The V flag is set when an overflow of a signed value occurs as a result of operation execution and is otherwise cleared. r C: Carry flag: The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation execution, and is otherwise cleared. s Register Bank Pointer (RP) The RP register indicates the relationship between the general-purpose registers of the F2MC16LX and the internal RAM addresses. Specifically, the RP register indicates the first memory address of the currently used register bank in the following conversion expression: [00180H + (RP)*10H] (see Figure 2.7-8). The RP register consists of five bits, and can take a value between 00H and 1FH. Register banks can be allocated at addresses from 000180H to 00037H in memory. Even within that range, however, the register banks cannot be used as general-purpose registers if the banks are not in internal RAM. The RP register is initialized to all zeroes by a reset. An instruction may transfer an eight-bit immediate value to the RP register; however, only the low-order five bits of that data are used. Figure 2.7-8 Register Bank Pointer (RP)
B4 Initial value 0 B3 0 B2 0 B1 0 B0 0 : RP
s Interrupt Level Mask Register (ILM) The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is accepted only when the level of the interrupt is higher than that indicated by these three bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.7-9). Therefore, for an interrupt to be accepted, its level value must be smaller than the current ILM value. When an interrupt is accepted, the level value of that interrupt is set in ILM. Thus, an interrupt of the same or lower level cannot be accepted subsequently. ILM is initialized to all zeroes by a reset. An instruction may transfer an eight-bit immediate value to the ILM register, but only the low-order three bits of that data are used. Figure 2.7-9 Interrupt Level Register (ILM)
ILM2 Initial value 0 ILM1 0 ILM0 0 : ILM
Table 2.7-1 Levels Indicated by the Interrupt Level Mask (ILM) Register ILM2 0 0 0 0 ILM1 0 0 1 1 ILM0 0 1 0 1 Level value 0 1 2 3 Acceptable interrupt level Interrupt disabled 0 only Level value smaller than 1 Level value smaller than 2
30
2.7 Registers Table 2.7-1 Levels Indicated by the Interrupt Level Mask (ILM) Register (Continued) ILM2 1 1 1 1 ILM1 0 0 1 1 ILM0 0 1 0 1 Level value 4 5 6 7 Acceptable interrupt level Level value smaller than 3 Level value smaller than 4 Level value smaller than 5 Level value smaller than 6
31
CHAPTER 2 CPU
2.7.4
Program Counter (PC)
The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU. The high-order eight bits of the address are indicated by the PCB. The PC register is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset. The PC register can also be used as a base pointer for operand access.
s Program Counter (PC) Figure 2.7-10 shows the program counter. Figure 2.7-10 Program Counter
PCB FE H PC ABCD H Next instruction to be executed FEABCD H
32
2.8 Register Bank
2.8
Register Bank
A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register bank can be used as instruction pointers.
s Register Bank Table 2.8-1 lists the functions of the registers. Table 2.8-2 indicates the relationship between the registers. In the same manner as for an ordinary RAM area, the register bank values are not initialized by a reset. The status before a reset is maintained. When the power is turned on, however, the register bank will have an undefined value. Table 2.8-1 Register Functions R0 to R7 Used as operands of instructions. Note: R0 is also used as a counter for barrel shift or normalization instructions. Used as pointers. Used as operands of instructions. Note: RW0 is used as a counter for string instructions. Used as long pointers. Used as operands of instructions.
RW0 to RW7
RL0 to RL3
Table 2.8-2 Relationship between Registers RW0 RL0 RW1 RW2 RL1 RW3 R0 RW4 R1 RL2 R2 RW5 R3 R4 RW6 R5 RL3 R6 RW7 R7
33
CHAPTER 2 CPU r Direct page register (DPR) DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown in Figure 2.8-1. DPR is eight bits long, and is initialized to 01H by a reset. DPR can be read or written to by an instruction. Figure 2.8-1 Generating a Physical address in Direct Addressing Mode
DTB register DPR register Direct address during instruction
MSB 24-bit physical address
LSB
r Program counter bank register (PCB) r Data bank register(DTB) r User stack bank register(USB) r System stack bank register(SSB) r Additional data bank register(ADB) Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is allocated. All bank registers are one byte long. PCB is initialized to 00H by a reset. Bank registers other than PCB can be read or written to. PCB can be read but cannot be written to. PCB is updated when the JMPP, CALLP, RETP, RETIQ, or RETF instruction branching to the entire 16-Mbyte space is executed or when an interrupt occurs. For operation of each register, see Section 2.2 "Memory space."
34
2.9 Prefix Codes
2.9
Prefix Codes
Placing a prefix code before an instruction partially changes the operation of the instruction. Three types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix.
s Bank Select Prefix The memory space used for accessing data is determined for each addressing mode. When a bank select prefix is placed before an instruction, the memory space used for accessing data by that instruction can be selected regardless of the addressing mode. Table 2.9-1 lists the bank select prefixes and the corresponding memory spaces. Table 2.9-1 Bank Select Prefix Bank select prefix PCB DTB ADB SPB Space selected PC space Data space AD space Either the SSP or USP space is used according to the stack flag value.
Use the following instructions with care: r String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) The bank register specified by an operand is used regardless of the prefix. r Stack manipulation instructions (PUSHW, POPW) SSB or USB is used according to the S flag regardless of the prefix. r I/O access instructions
MOV A, io / MOV io, A /MOVX A, io / MOVW A, io /MOVW io, A / MOV io, #imm8 MOV io, #imm16 / MOVB A, io:bp / MOB io:bp, A /SETB io:bp / CLRB io:bp BBC io:bp, rel / BBS io:bp, rel WBTC, WBTS
The IO space of the bank is used regardless of the prefix. r Flag change instructions (AND CCR,#imm8, OR CCR,#imm8) The instruction is executed normally, but the prefix affects the next instruction. r POPW PS SSB or USB is used according to the S flag regardless of the prefix. The prefix affects the next instruction.
35
CHAPTER 2 CPU r MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. r RETI SSB is used regardless of the prefix. s Common Register Bank Prefix (CMR) To simplify data exchange between multiple tasks, the same register bank must be accessed relatively easily regardless of the RP value. When CMR is placed before an instruction that accesses a register bank, that instruction accesses the common bank (the register bank selected when RP=0) at addresses from 000180H to 00018FH regardless of the current RP value. Use the following instructions with care: r String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string instruction is executed falsely after the interrupt is processed. Do not prefix any of the above string instructions with CMR. r Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS) The instruction is executed normally, but the prefix affects the next instruction. r MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. s Flag Change Disable Prefix (NCC) To disable flag changes, use the flag change disable prefix code (NCC). Placing NCC before an instruction disables flag changes associated with that instruction. Use the following instructions with care: r String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string instruction is executed incorrectly after the interrupt is processed. Do not prefix any of the above string instructions with NCC. r Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS) The instruction is executed normally, but the prefix affects the next instruction. r Interrupt instructions (INT #vct8, INT9, INT addr16, INTP addr24, RETI) CCR changes according to the instruction specifications regardless of the prefix. r JCTX @A CCR changes according to the instruction specifications regardless of the prefix. r MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction.
36
2.10 Interrupt Disable Instructions
2.10 Interrupt Disable Instructions
Interrupt requests are not sampled for the following ten instructions: - MOV ILM,#imm8 - PCB - SPB - OR CCR,#imm8 - AND CCR,#imm8 - ADB - CMR - POPW PS
- NCC - DTB
s Interrupt Disable Instructions If a valid interrupt request occurs during execution of any of the above instructions, the interrupt can be processed only when an instruction other than the above is executed. For details, see Figure 2.10-1. Figure 2.10-1 Interrupt Disable Instruction
Interrupt disable instruction
********
(a)
***
(a) Ordinary instruction
Interrupt request
Interrupt acceptance
s Restrictions on Interrupt Disable Instructions and Prefix Instructions When a prefix code is placed before an interrupt disable instruction, the prefix code affects the first instruction after the code other than the interrupt disable instruction. For details, see Figure 2.10-2. Figure 2.10-2 Interrupt Disable Instructions and Prefix Codes
Interrupt disable instruction
MOV A, FF H CCR:XXX10XX
NCC
MOV ILM,#imm8
****
ADD A,01
H
CCR:XXX10XX CCR does not change with NCC.
s Consecutive Prefix Codes When competitive prefix codes are placed consecutively, the latter becomes valid. In the figure below, competitive prefix codes are PCB, ADB, DTB, and SPB. For details, see Figure 2.10-3. Figure 2.10-3 Consecutive Prefix Codes
Prefix code
*****
ADB
DTB
PCB
A D D A , 0 1H
****
PCB is valid as the prefix code
37
CHAPTER 2 CPU
38
CHAPTER 3
INTERRUPTS
This chapter explains the interrupt functions and operations. 3.1 Outline of Interrupts 3.2 Interrupt Vector 3.3 Interrupt Control Registers (ICR) 3.4 Interrupt Flow 3.5 Hardware Interrupts 3.6 Software Interrupts 3.7 Extended Intelligent I/O Service (EI2OS) 3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) 3.9 Exceptions
39
CHAPTER 3 INTERRUPTS
3.1
Outline of Interrupts
The F2MC-16LX has interrupt functions that terminate the currently executing processing and transfer control to another specified program when a specified event occurs. There are four types of interrupt functions: * Hardware interrupt: Interrupt processing due to an internal resource event * Software interrupt: Interrupt processing due to a software event occurrence instruction * Extended intelligent I/O service (EI2OS): Transfer processing due to an internal resource event * Exception: Termination due to an operation exception
s Hardware Interrupts A hardware interrupt is activated by an interrupt request from an internal resource. A hardware interrupt request occurs when both the interrupt request flag and the interrupt enable flag in an internal resource are set. Therefore, an internal resource must have an interrupt request flag and interrupt enable flag to issue a hardware interrupt request. r Specifying an interrupt level An interrupt level can be specified for the hardware interrupt. To specify an interrupt level, use the level setting bits (IL0, IL1, and IL2) of the interrupt controller. r Masking a hardware interrupt request A hardware interrupt request can be masked by using the I flag of the processor status register (PS) in the CPU and the ILM bits (IL0, IL1, and IL2). When an unmasked interrupt request occurs, the CPU saves 12 bytes of data that consists of registers PS, PC, PCB, DTB, ADB, DPR, and A in the memory area indicated by the SSB and SSP registers. Figure 3.1-1 Overview of Hardware Interrupts
Register file Microcode F2MC-16 bus F 2 M C - 1 6 LX * C P U Peripheral IR PS I Check ILM
Comparator Level comparator Interrupt level IL PS I ILM IR : : : : Processor status Interrupt enable flag Interrupt level mask register Instruction register
Enable FF
AND
Cause FF
Interrupt controller
s Software Interrupts Interrupts requested by executing the INT instruction are software interrupts. An interrupt
40
3.1 Outline of Interrupts request by the INT instruction does not have an interrupt request or enable flag. An interrupt request is issued always by executing the INT instruction. No interrupt level is assigned to the INT instruction. Therefore, ILM is not updated when the INT instruction is used. Instead, the I flag is cleared and the continuing interrupt requests are suspended. Figure 3.1-2 Overview of Software Interrupts
Register file F2MC-16 bus Microcode F 2 M C - 1 6 LX * C P U Save Instruction bus IR Queue PS I S B unit Fetch
PS I ILM IR B unit : : : : : Processor status Interrupt enable flag Interrupt level mask register Instruction register Bus interface unit
RAM
s Extended Intelligent I/O Service (EI2OS) The extended intelligent I/O service automatically transfers data between an internal resource and memory. This processing is traditionally performed by an interrupt processing program, but the EI2OS enables data to be transferred in a manner similar to a DMA (direct memory access) operation. To activate the extended intelligent I/O service function from an internal resource, the interrupt control register (ICR) of the interrupt controller must have an extended intelligent I/O service enable flag (ISE). The extended intelligent I/O service is started when an interrupt request occurs with 1 specified in the ISE flag. To generate a normal interrupt using a hardware interrupt request, set the ISE flag to 0.
41
CHAPTER 3 INTERRUPTS Figure 3.1-3 Overview of the Extended Intelligent I/O Service (EI2OS)
Memory space by IOA I/O register CPU z z ISD by ICS y I/O register Peripheral x
Interrupt request
Interrupt control register Interrupt controller
by BAP { Buffer
x I/O requests transfer. y The interrupt controller selects the descriptor. z The transfer source and destination are read from the descriptor. by DCT { Data is transferred between I/O and memory.
s Exceptions Exception processing is basically the same as interrupt processing. When an exception is detected between instructions, exception processing is performed. In general, exception processing occurs as a result of an unexpected operation. Therefore, use exception processing only for debugging programs or for activating recovery software in an emergency.
42
3.2 Interrupt Vector
3.2
Interrupt Vector
An interrupt vector uses the same area for both hardware and software interrupts. For example, interrupt request number INT42 is used for a delayed hardware interrupt and for software interrupt INT #42. Therefore, the delayed interrupt and INT #42 call the same interrupt processing routine. Interrupt vectors are allocated between addresses FFFC00H and FFFFFFH as shown in Table 3.2-1.
s Interrupt Vector
Table 3.2-1 Interrupt Vectors Interrupt request INT 0*1 INT 1*1 . . . INT 7*1 INT 8*2 INT 9 INT 10*3 INT 11 . . . INT 254 INT 255 Vector address L FFFFFCH FFFFF8H . . . FFFFE0H FFFFDCH FFFFD8H FFFFD4H FFFFD0H . . . FFFC04H FFFC00H Vector address H FFFFFDH FFFFF9H . . . FFFFE1H FFFFDDH FFFFD9H FFFFD5H FFFFD1H . . . FFFC05H FFFC01H Vector address bank FFFFFEH FFFFFAH . . . FFFFE2H FFFFDEH FFFFDAH FFFFD6H FFFFD2H . . . FFFC06H FFFC02H Mode register Unused Unused . . . Unused FFFFDFH Unused Unused Unused . . . Unused Unused
*1: When PCB is FFH, the vector area for the CALLV instruction is the same as that for INT #vct8(#0 to #7). Care must be taken when using the vector for the CALLV instruction. *2: The vector is a reset vector. *3: The vector is an exception processing vector. s Listing of Interrupt Vectors See Table C-1 in Appendix C for a list of the MB90590 interrupt vectors.
43
CHAPTER 3 INTERRUPTS
3.3
Interrupt Control Registers (ICR)
The interrupt control registers are in the interrupt controller. Each interrupt control register has a corresponding I/O that has an interrupt function. The interrupt control registers have the following three functions: * Setting an interrupt level for corresponding peripherals * Selecting whether to use an ordinary interrupt or extended intelligent I/O service for the corresponding peripherals * Selecting the extended intelligent I/O service channel Do not access an interrupt control register by using a read-modify-write instruction, as doing so causes a misoperation.
s Interrupt Control Register (ICR) Figure 3.3-1 is a diagram of the bit configuration of an interrupt control register. Figure 3.3-1 Interrupt Control Register (ICR)
15/7 ICS3 14/6 ICS2 13/5 ICS1 or S1 12/4 ICS0 or S0 11/3 ISE 10/2 IL2 9/1 IL1 8/0 IL0 Interrupt control register 00000111 B when reset
W
W
*
*
R/W
R/W
R/W
R/W
Note: ICS3 to ICS0 are valid only when EI2OS is activated. Set '1' in ISE to activate EI2OS, and set
'0' in ISE not to activate it. When EI2OS is not to be activated, any value can be set in ICS3 to ICS0. * '1' is read always.
ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only. [bits 10 to 8] [bits 2 to 0]: IL0, IL1, and IL2 (interrupt level setting bits) These bits are readable and writable, and specify the interrupt level of the corresponding internal resources. Upon a reset, these bits are initialized to level 7 (no interrupt). Table 3.3-1 describes the relationship between the interrupt level setting bits and interrupt levels. Table 3.3-1 Interrupt Level Setting Bits and Interrupt Levels ILM2 0 0 0 0 1 1 ILM1 0 0 1 1 0 0 ILM0 0 1 0 1 0 1 0 (Strongest) 1 2 3 4 5 Level
44
3.3 Interrupt Control Registers (ICR) Table 3.3-1 Interrupt Level Setting Bits and Interrupt Levels (Continued) ILM2 1 1 ILM1 1 1 ILM0 0 1 6 (Weakest) 7 (No interrupt) Level
[bit 11] [bit 3]: ISE (extended intelligent I/O service enable bits) The ISE bit is readable and writable. In response to an interrupt request, EI2OS is activated when '1' is set in the ISE bit and an interrupt sequence is activated when '0' is set in the ISE bit. Upon completion of EI2OS, the ISE bit is cleared to a zero. If the corresponding peripheral does not have the EI2OS function, the ISE bit must be set to '0' on the software side. Upon a reset, the ISE bit is initialized to '0.' [bits 15 to 12] [bits 7 to 4]: ICS 3 to 0 (extended intelligent I/O service channel select bits) ICS3 to ICS0 are write-only bits. These bits specify the EI2OS channel. The values set in these bits determined the intelligent I/O service descriptor addresses in memory, which is explained later. The ICS bits are initialized by a reset. Table 3.3-2 describes the correspondence between the ICS bits, channel numbers, and descriptor addresses.
45
CHAPTER 3 INTERRUPTS
Table 3.3-2 ICS bits, Channel Numbers, and Descriptor Addresses ICS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ICS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ICS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ICS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selected channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Descriptor address 000100H 000108H 000110H 000118H 000120H 000128H 000130H 000138H 000140H 000148H 000150H 000158H 000160H 000168H 000170H 000178H
[bits 13 and 12] [bits 5 and 4]: S0 and S1 (extended intelligent I/O service status) S0 and S1 are read-only bits. The values set in these bits indicate the end condition of EI2OS. These bits are initialized to '00' upon a reset. Table 3.3-3 shows the relationship between the S bits and the end conditions. Table 3.3-3 S Bits and End Conditions S1 0 0 1 1 S0 0 1 0 1 End condition EI2OS running or not activated Termination by count Reserved Termination by request from resource
46
3.4 Interrupt Flow
3.4
Interrupt Flow
Figure 3.4-1 shows the interrupt flow.
s Interrupt Flow
Figure 3.4-1 Interrupt Flow
I ILM IF IE Flag in CCR Level register in CPU Internal resource interrupt request Internal resource interrupt enable flag ISE : EI 2 OS enable flag IL : Internal resource interruptrequest level S : Flag in CCR : : : :
I & IF & IE = 1 AND ILM > IL NO
YES
NO ISE = 1
YES
Fetching and decoding the next instruction Saving PS, PC, PCB, DTB, ADB, DPR, and A into the stack of SSP, and setting ILM=IL Executing the extended intelligent I/O service
YES INT instruction
NO Executing an ordinary instruction Saving PS, PC, PCB, DTB, ADB, DPR, and A into the stack of SSP, and setting I=O and ILM=IL
NO
Completion of string instruction repetition YES
S 1 Fetching the interrupt vector
Updating PC
47
CHAPTER 3 INTERRUPTS Figure 3.4-2 Register Saving during Interrupt Processing
Word (16 bits) MSB H LSB SSP (SSP value before interrupt) AH AL DPR DPB PC PS L SSP (SSP value after interrupt) ADB PCB
48
3.5 Hardware Interrupts
3.5
Hardware Interrupts
In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user. This function is called the hardware interrupt function.
s Hardware Interrupts A hardware interrupt occurs when the relevant conditions are satisfied as a result of two operations: comparison between the interrupt request level and the value in the interrupt level mask register (ILM) of PS in the CPU, and hardware reference to the I flag value of PS. The CPU performs the following processing when a hardware interrupt occurs: * * * Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system stack. Sets ILM in the PS register. The currently requested interrupt level is automatically set. Fetches the corresponding interrupt vector value and branches to the processing indicated by that value.
s Structure of Hardware Interrupt Hardware interrupts are handled by the following three sections: r Internal resources Interrupt enable and request bits: Used to control interrupt requests from resources. r Interrupt controller ICR: Assigns interrupt levels and determines the priority levels of simultaneously requested interrupts. r CPU I and ILM: Used to compare the requested and current interrupt levelsand to identify the interrupt enable status. Microcode: Interrupt processing step The status of these sections are indicated by the resource control registers for internal resources, the ICR for the interrupt controller, and the CCR value for the CPU. To use a hardware interrupt, set the three sections beforehand by using software. The interrupt vector table referenced during interrupt processing is assigned to addresses FFFC00H to FFFFFFH in memory. These addresses are shared with software interrupts.
49
CHAPTER 3 INTERRUPTS
3.5.1
Hardware Interrupt Operation
An internal resource that has the hardware interrupt request function has an interrupt request flag and interrupt enable flag. The interrupt request flag indicates whether an interrupt request exists, and the interrupt enable flag indicates whether the relevant internal resource requests an interrupt to the CPU. The interrupt request flag is set when an event occurs that is unique to the internal resource. When the interrupt enable flag indicates "enable," the resource issues an interrupt request to the interrupt controller.
s Hardware Interrupt Operation When two or more interrupt requests are received at the same time, the interrupt controller compares the interrupt levels (IL) in ICR, selects the request at the highest level (the smallest IL value), then reports that request to the CPU. If multiple requests are at the same level, the interrupt controller selects the request with the lowest interrupt number. The relationship between the interrupt requests and ICRs is determined by the hardware. The CPU compares the received interrupt level and the ILM in the PS register. If the interrupt level is smaller than the ILM value and the I bit of the PS register is set to 1, the CPU activates the interrupt processing microcode after the currently executing instruction is completed. The CPU references the ISE bit of the ICR of the interrupt controller at the beginning of the interrupt processing microcode, checks that the ISE bit is 0 (interrupt), and activates the interrupt processing body. The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP, fetches three bytes of interrupt vector and loads them onto PC and PCB, updates the ILM of PS to a level value of the received interrupt, sets the S flag, then performs branch processing. As a result, the interrupt processing program defined by the user is executed next. Figure 3.5-1 illustrates the flow from the occurrence of a hardware interrupt until there is no interrupt request in the interrupt processing program.
50
3.5 Hardware Interrupts
3.5.2
Occurrence and Release of Hardware Interrupt
Figure 3.5-1 shows the processing flow from occurrence of a hardware interrupt to release of the interrupt request in an interrupt processing program.
s Occurrence and Release of Hardware Interrupt
Figure 3.5-1 Occurrence and Release of Hardware Interrup
Register file Microcode
F2MC-16 bus
PS IR
I Check
ILM
Comparator
PS I ILM IR
: : : :
Processor status Interrupt enable flag Interrupt level mask register Instruction register
F 2 M C - 1 6 LX * C P U Peripheral
Level comparator
Enable FF
AND
Cause FF
Interrupt level IL
Interrupt controller
1. An interrupt cause occurs in a peripheral. 2. The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, the peripheral issues an interrupt request to the interrupt controller. 3. Upon reception of the interrupt request, the interrupt controller determines the priority levels of simultaneously requested interrupts. Then, the interrupt controller transfers the interrupt level of the corresponding interrupt to the CPU. 4. The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of the processor status register. 5. If the comparison shows that the requested level is higher than the current interrupt processing level, the I flag value of the same processor status register is checked. 6. If the check in step 5. shows that the I flag indicates interrupt enable status, the requested level is written to the ILM bit. Interrupt processing is performed as soon as the currently executing instruction is completed, then control is transferred to the interrupt processing routine. 7. When the interrupt cause of step 1. is cleared by software in the user interrupt processing routine, the interrupt request is completed. The time required for the CPU to execute the interrupt processing in steps 6. and 7. is shown below. Interrupt start: 24 + 6
x (Table 3.3.2 machine cycles)
Interrupt return: 15 + 6 x (Table 3.3.2 machine cycles) RETI instruction
51
CHAPTER 3 INTERRUPTS Table 3.5-1 Compensation Values for Interrupt Processing Cycle Count Address indicated by the stack pointer External area, 8-bit data bus External area, even-numbered address External area, odd-numbered address Internal area, even-numbered address Internal area, odd-numbered address Cycle count compensation value +4 +1 +4 0 +2
52
3.5 Hardware Interrupts
3.5.3
Multiple interrupts
As a special case, no hardware interrupt request can be accepted while data is being written to the I/O area. This is intended to prevent the CPU from operating falsely because of an interrupt request issued while an interrupt control register for a resource is being updated. If an interrupt occurs during interrupt processing, a higher-level interrupt is processed first.
s Multiple Interrupts The F2MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while another interrupt is being processed, control is transferred to the high-level interrupt after the currently executing instruction is completed. After processing of the high-level interrupt is completed, the original interrupt processing is resumed. An interrupt of the same or lower level may be generated while another interrupt is being processed. If this happens, the new interrupt request is suspended until the current interrupt processing is completed, unless the ILM value or I flag is changed by an instruction. The extended intelligent I/O service cannot be activated from multiple sources; while an extended intelligent I/O service is being processed, all other interrupt requests or extended intelligent I/O service requests are suspended. Figure 3.5-2 shows the order of the registers saved in the stack. Figure 3.5-2 Registers Saved in Stack
Word (16 bits)
MSB H
LSB
SSP (SSP value before interrupt) AH AL DPR DPB PC PS L SSP (SSP value after interrupt) ADB PCB
53
CHAPTER 3 INTERRUPTS
3.6
Software Interrupts
In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. This is called the software interrupt function. A software interrupt occurs always when the software interrupt instruction is executed.
s Software Interrupts The CPU performs the following processing when a software interrupt occurs: * * * Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system stack. Sets I in the PS register. Interrupts are automatically disabled. Fetches the corresponding interrupt vector value, then branches to the processing indicated by that value.
A software interrupt request issued by the INT instruction has no interrupt request or enable flag. A software interrupt request is always issued by executing the INT instruction. The INT instruction does not have an interrupt level. Therefore, the INT instruction does not update ILM. The INT instruction clears the I flag to suspend subsequent interrupt requests. s Structure of Software Interrupts Software interrupts are handled within the CPU: CPU.....Microcode: Interrupt processing step s List of MB90590 Interrupt Vectors Table D-1 lists the interrupt vectors of the MB90590 series. As shown in Table D-1, software interrupts share the same interrupt vector area with hardware interrupts. For example, interrupt request number INT 13 is used for external interrupt #0 of a hardware interrupt as well as for INT #13 of a software interrupt. Therefore, external interrupt #0 and INT #13 call the same interrupt processing routine. s Software Interrupt Operation When the CPU fetches and executes the software interrupt instruction, the software interrupt processing microcode is activated. The software interrupt processing microcode saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The microcode then fetches three bytes of interrupt vector and loads them onto PC and PCB, resets the I flag, and sets the S flag. Then, the microcode performs branch processing. As a result, the interrupt processing program defined by the user application program is executed next. Figure 3.6-1 illustrates the flow from the occurrence of a software interrupt until there is no interrupt request in the interrupt processing program.
54
3.6 Software Interrupts Figure 3.6-1 Occurrence and Release of Software Interrupt
Register file PS I S B unit IR Queue Fetch
F2MC-16 bus Microcode
PS : Processor status I : Interrupt enable flag ILM : Interrupt level mask registe IR : Instruction register B unit: Bus interface unit
F 2 M C - 1 6 LX * C P U
Save
Instruction bus
RAM
1. The software interrupt instruction is executed. 2. Special CPU registers in the register file are saved according to the microcode corresponding to the software interrupt instruction. 3. The interrupt processing is completed with the RETI instruction in the user interrupt processing routine. s Others When the program bank register (PCB) is FFH, the CALLV instruction vector area overlaps the table of the INT #vct8 instruction. When designing software, ensure that the CALLV instruction does not use the same address as that of the #vct8 instruction. Table D-2 shows the relationship of interrupt cause, interrupt vector, and interrupt control register in the MB90590 series.
55
CHAPTER 3 INTERRUPTS
3.7
Extended Intelligent I/O Service (EI2OS)
The EI2OS function automatically transfers data between input and output and memory. An interrupt processing program was conventionally used for such processing, but EI2OS enables data transfer to be performed like DMA (direct memory access).
s Extended Intelligent I/O Service (EI2OS) EI2OS has the following advantages over the conventional method: * * * * * The program size can be small because it is not necessary to write a transfer program. No internal register is used for transfer, eliminating the need for register saving and increasing the transfer speed. Transfer can be terminated from I/O, preventing unnecessary data from being transferred. The buffer address may either be incremented or left unupdated. The I/O register address may either be incremented or left unupdated.
At the end of EI2OS, processing automatically branches to an interrupt processing routine after the end condition is set. Thus, the user can identify the end condition. To implement EI2OS, the hardware is distributed in two blocks. Each block has the following registers and descriptors. r Interrupt control register: Exists in the interrupt controller and indicates the ISD address. r Extended intelligent I/O service descriptor (ISD): Exists in RAM and holds the transfer mode, I/O address, number of transfers, and buffer address. Figure 3.7-1 outlines the extended intelligent I/O service.
56
3.7 Extended Intelligent I/O Service (EI2OS) Figure 3.7-1 Outline of Extended Intelligent I/O Service
Memory space by IOA I/O register CPU Interrupt request ISD by ICS
*** *** *** *** ***
I/O register
Peripheral
Interrupt control register Interrupt controller
by BAP
x I/O requests transfer. y The interrupt controller selects the
descriptor. Buffer by DCT
z The transfer source and destination
are read from the descriptor.
{ Data is transferred between I/O and
memory.
Note: The area that can be specified by IOA is between 000000H and 00FFFFH. The area that can be specified by BAP is between 000000H and FFFFFFH. The maximum transfer count that can be specified by DCT is 65,536. s Structure EI2OS is handled by the following four sections: Internal resources Interrupt enable and request bits: Used to control interrupt requests from resources. Interrupt controller ICR: Assigns interrupt levels, determines the priority levels of simultaneously requested interrupts, and selects the EI2OS operation. CPU I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt enable status Microcode: EI2OS processing step RAM Descriptor: Describes the EI2OS transfer information. .
57
CHAPTER 3 INTERRUPTS
3.7.1
Extended Intelligent I/O Service Descriptor (ISD)
The extended intelligent I/O service descriptor exists between 000100H and 00017FH in internal RAM, and consists of the following items: * Data transfer control data * Status data * Buffer address pointer
s Extended Intelligent I/O Service Descriptor (ISD) Figure 3.7-2 shows the configuration of the extended intelligent I/O service descriptor. Figure 3.7-2 Extended Intelligent I/O Service Descriptor Configuration
High-order 8 bits of data counter (DCTH) Low-order 8 bits of data counter (DCTL) High-order 8 bits of I/O address pointer (IOAH) Low-order 8 bits of I/O address pointer (IOAL) EI 2OS status (ISCS) High-order 8 bits of buffer address pointer (BAPH) 000100 H + 8 x ICS ISD start address
s Data Counter (DCT)
H
Medium-order 8 bits of buffer address pointer (BAPM) Low-order 8 bits of buffer address pointer (BAPL)
L
This is a 16-bit register that works as a counter corresponding to the number of data items transferred. This counter is decremented by one before data transfer. EI2OS is terminated when this counter reaches 0. Figure 3.7-3 is a diagram of the data counter configuration. Figure 3.7-3 Data Counter Configuration
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 DCT (Undefined when reset)
B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00
s I/O Register Address Pointer (IOA)
This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer and I/O register used for data transfer. The high-order address (A23 to A16) are all zeroes, and any I/O between addresses 000000H and 00FFFFH can be specified. Figure 3.7-4 is a diagram of the IOA configuration.
58
3.7 Extended Intelligent I/O Service (EI2OS) Figure 3.7-4 I/O Register Address Pointer Configuration
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 IOA (Undefined when reset)
A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
s Buffer Address Pointer (BAP)
This 24-bit register holds the address used for the next EI2OS transfer. BAP exists for each EI2OS channel. Therefore, each EI2OS channel can be used for transfer with anywhere in the 16-Mbyte space. If the BF bit of ISCS is set to '0' (update enabled), only the low-order 16 bits of BAP changes and BAPH does not change.
59
CHAPTER 3 INTERRUPTS
3.7.2
EI2OS Status Register (ISCS)
This eight-bit register indicates the update direction (increment/decrement), transfer data format (byte/word), and transfer direction of the buffer address pointer and the I/O register address pointer. This register also indicates whether the buffer address pointer or I/O register address pointer is updated or fixed.
s EI2OS Status Register (ISCS) Figure 3.7-5 is a diagram of the ISCS configuration. Figure 3.7-5 ISCS Configuration
7 6 5 4 IF 3 BW 2 BF 1 DIR 0 SE ISCS (Undefined when reset)
Reserved Reserved Reserved
* Always write 0 to bits 7 to 5 of ISCS. Each bit is described below. [bit 4] IF : 0: 1: [bit 3] BW : 0: 1: [bit 2] BF : 0: 1: [bit 1] DIR : 0: 1: [bit 0] SE : 0: 1: Specify whether the I/O register address pointer is updated or fixed. The I/O register address pointer is updated after data transfer. The I/O register address pointer is not updated after data transfer. Only increment is allowed. Specify the transfer data length. Byte Word Specify whether the buffer address pointer is updated or fixed. The buffer address pointer is updated after data transfer. The buffer address pointer is not updated after data transfer. Only the low-order 16 bits of the buffer address are updated. Only increment is allowed. Specify the data transfer direction. I/O --> Buffer Buffer --> I/O Control the termination of the extended intelligent I/O service based on resource requests. The extended intelligent I/O service is not terminated by a resource request. The extended intelligent I/O service is terminated by a resource request.
60
3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS)
3.8
Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS)
Figure 3.8-1 is a diagram of the EI2OS operation flow. Figure 3.8-2 is a diagram of the EI2OS use procedure.
s EI2OS Operation Flow
Figure 3.8-1 EI2OS Operation Flow
BAP I/OA ISD ISCS DCT ISE S1 and S0 NO Interrupt sequence : : : : : : : Buffer address pointer I/O address pointer EI 2OS descriptor EI2 OS status Data counter EI2OS enable bit EI2OS end status
Interrupt request issued from internal resource
ISE = 1 YES Reading ISD/ISCS
End request from resource NO
YES SE = 1
DIR = 1 NO
YES
Data indicated by IOA (Data transfer) Memory indicated by BAP YES
Data indicated by BAP (Data transfer) Memory indicated by IOA
IF = 0 NO
Update value depends on BW. YES Update value depends on BW.
Updating IOA
BF = 0 NO
Updating BAP
Decrementing DCT DCT = 00 NO Setting S1 and S0 to '00' YES Setting S1 and S0 to '01' Setting S1 and S0 to '11'
Clearing resource interrupt request
Clearing ISE to '0'
CPU operation return
Interrupt sequence
61
CHAPTER 3 INTERRUPTS Figure 3.8-2 EI2OS Use Flow
Processing by CPU EI2OS initialization (Interrupt request) AND (ISE = 1) Normal termination Processing by EI2OS
JOB execution
Data transfer
Re-setting of extended intelligent I/O service (Switching channels) Processing data in buffer
The extended EI2OS execution time for each flow is described below. r When data transfer continues (when the stop condition is not satisfied) (Table 3.8-1 + Table 3.8-2) machine cycles r When a stop request is issued from a resource (36 + 6 x Table 3.D-2) machine cycles r When the counting is completed (Table 3.8-1 + Table 3.8-2 + (21 + 6 x Table 3.D-2)) machine cycles Table 3.8-1 Execution Time when the Extended EI2OS Continues ISCS SE bit I/O address pointer Fixed Buffer address pointer Updated 34 36 35 37 Set to '0' Fixed 32 Updated 34 Set to '1' Fixed 33 Updated 35
Table 3.8-2 Data Transfer Compensation Values for Extended EI2OS Execution Time Internal access I/O address pointer B/E Internal access Buffer address pointer External access B: Byte data transfer E: Even address word transfer 62 B/E 8/O +1 +4 +3 +6 +2 +5 +5 +8 B/E O 0 +2 O +2 +4 B/E +1 +3 8/O +4 +6 External access
3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) 8: 8-bit external bus word transfer O: Odd address word transfer
63
CHAPTER 3 INTERRUPTS
3.9
Exceptions
The F2MC-16LX performs exception processing when the following event occurs:
s Execution of an Undefined Instruction Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Fujitsu recommends using exception processing only for debugging or for activating emergency recovery software. s Exception due to Execution of an Undefined Instruction The F2MC-16LX handles all codes that are not defined in the instruction map as undefined instructions. When an undefined instruction is executed, processing equivalent to the INT 10 software interrupt instruction is performed. Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC, and PS values are saved into the system stack, and processing branches to the routine indicated by the interrupt number 10 vector. In addition, the I flag is cleared and the S flag is set. The PC value saved in the stack is the address at which the undefined instruction is stored. Processing can be restored by the RETI instruction, but is of no use, however, because the same exception occurs again.
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CHAPTER 4
DELAYD INTERRUPT
This chapter explains the functions and operations of the delayed interrupt. 4.1 Outline of Delayed Interrupt Module 4.2 Delayed Interrupt Register 4.3 Delayed Interrupt Operation
65
CHAPTER 4 DELAYD INTERRUPT
4.1
Outline of Delayed Interrupt Module
The delayed interrupt source module is used to generate interrupts for switching tasks. Using this module, interrupt requests to the F2MC-16LX CPU can be issued and canceled by software.
s Block Diagram of Delayed Interrupt Figure 4.1-1 is a block diagram of the delayed interrupt source module. Figure 4.1-1 Block Diagram
F2MC-16 bus Delayed interrupt cause issuance/cancellation decoder
Cause latch
s Notes on Operation This lock is set by writing '1' to the corresponding bit of DIRR, and is cleared by writing '0' to the same bit. Therefore, interrupt processing is reactivated immediately after control returns from interrupt processing, unless the software is designed so that the cause of the interrupt is cleared within the interrupt processing routine.
66
4.2 Delayed Interrupt Register
4.2
Delayed Interrupt Register
DIRR controls issuance and cancellation of delayed interrupt requests. Writing "1" to this register issues a delayed interrupt request, and writing "0" cancels the delayed interrupt request. Upon a reset, the request is canceled.
s Delayed Interrupt Cause Issuance/Cancellation Register (DIRR: Delayed Interrupt Request Register) In DIRR, either "0" or "1" can be written to the reserved bit area. However, it is recommended that a set bit or clear bit instruction be used to access this register for future expansions.
15 DIRR
Address: 00009F H
14 -
13 -
12 -
11 -
10 -
9 -
8 R0 R/W --------0 B
-
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CHAPTER 4 DELAYD INTERRUPT
4.3
Delayed Interrupt Operation
When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the delayed interrupt source module is set and an interrupt request is issued to the interrupt controller.
s Delayed Interrupt Occurrence When the CPU writes '1' to the relevant bit of DIRR by software, the request latch in the delayed interrupt source module is set and an interrupt request is issued to the interrupt controller. If this interrupt has the highest priority or if there is no other interrupt request, the interrupt controller issues an interrupt request to the F2MC-16LX CPU. The F2MC-16LX CPU compares the ILM bit of its internal CCR register and the interrupt request, and starts the hardware interrupt processing microprogram as soon as the current instruction is completed if the interrupt level of the request is higher than that of the ILM bit. The interrupt processing routine for this interrupt is thus executed. Figure 4.3-1 Delayed Interrupt Issuance
Delayed interrupt source module
WRITE
Interrupt controller
F2MC-16LX CPU
Other requests ICR yy
CMP
IL
CMP
DDIR
ICR xx
ILM NTA
68
CHAPTER 5
CLOCK AND RESET
This chapter explains the functions and operations of clocks and resets. 5.1 Clock Generator 5.2 Reset Cause Occurrence 5.3 Reset Causes
69
CHAPTER 5 CLOCK AND RESET
5.1
Clock Generator
The clock generator controls internal clock operation, including such functions as sleep, timer, stop, and PLL multiplication. This internal clock is called the machine clock, and one cycle of the machine clock is called a machine cycle. A clock based on the source oscillation is called the main clock, and a clock based on the internal VCO oscillation is called the PLL clock.
s Notes on Clock Generator When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz and 16 MHz. The highest operating frequency for the CPU and peripheral resource circuits is 16 MHz, however. Normal operation is not guaranteed if a multiplication factor resulting in a higher frequency than 16 MHz is specified. For example, if the source oscillation is 16 MHz, only 1 can be specified as the multiplication factor. The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation below 4 MHz must not be specified. Figure 5.1-1 is a block diagram of the clock generator circuit. Figure 5.1-1 Clock Generator Circuit Block Diagram
SQ Reset Interrupt HSTX Transition to stop mode SQ R Transition to timer or sleep mode R SQ R 1 2 3 4 PLL multiplication
Machine clock Selecting the machine clock
Selecting the oscillation stabilization wait time Time base timer 1/2 X0 XL Selecting the watch-dog timer interval Monitoring timer Watch-dog reset 1/2048 1/4 1/4 1/8
70
5.2 Reset Cause Occurrence
5.2
Reset Cause Occurrence
When a reset cause occurs, F2MC-16LX terminates the currently executing processing and waits for reset release. A reset is caused by the following factors:
s Reset Cause Occurrence A reset is caused by the following factors: * * * * * Power-on reset Hardware standby release Watch-dog timer overflow External reset request via RSTX pin Reset request by software
While an external bus is used, the address generated by the device is undefined when a reset cause occurs. All external bus access signals, including RDX and WRX, become inactive. s Operation after Reset Release When a reset cause is removed, the F2MC-16LX immediately outputs the address in which the reset vector is stored, then fetches the reset vector and mode data. The reset vector and mode data are assigned to the four bytes between FFFFDCH and FFFFDFH. After reset is released, the reset vector and mode data are transferred to the registers by the hardware as described in Figure 5.2-1. Use the mode pin to specify whether to read the reset vector and mode data from internal ROM or from external memory. When the mode pin is set to external vector mode, the F2MC-16LX reads the reset vector and mode data from external memory. When using the F2MC-16LX in single chip mode or internal ROM external bus mode, Fujitsu recommends specifying internal vector mode. The bus mode after the reset vector and mode data are read is specified by the mode data.
71
CHAPTER 5 CLOCK AND RESET Figure 5.2-1 Source and Destination of Reset Vector and Mode Data
F2MC-16LX CPU Mode Memory space Register FFFFDFH FFFFDEH FFFFDD H FFFFDCH Mode data Reset vector bits 23 to 16 Reset vector bits 15 to 8 Reset vector bits 7 to 0 Micro ROM Reset sequence
PCB PC
Note: For MB90F594, the reset vector and mode data have predetermined values by the hardwired logic. For more information, refer to "Reset Vector Addesses in Flash Memory".
72
5.3 Reset Causes
5.3
Reset Causes
Table 5.3-1 lists the five reset causes. The machine clock and watch-dog function are initialized differently for each reset cause. The reset cause register indicates the reset cause.
s Reset Causes
Table 5.3-1 Reset Causes Reset Power-on Hardware standby Watch-dog timer External pin Software Cause When the power is turned on 'L' level input to HSTX pin Watch-dog timer overflow 'L' level input to RSTX pin '0' written to RST bit of STBYC Machine clock Main clock Main clock Main clock Previous status maintained Previous status maintained Watch-dog timer Stop Stop Stop Previous status maintained Previous status maintained Oscillation stabilization wait Yes Yes Yes No No
* In stop or hardware standby mode, a reset input allows for oscillation stabilization time regardless of the reset cause. * The oscillation stabilization time for a power-on reset is fixed to 218 cycles of source oscillation. For other types of reset, the oscillation stabilization wait time is determined by CS1 and CS0 of the clock selection register. As shown in Figure 5.3-1, each reset cause has a corresponding flip-flop. The contents of the flip-flop can be obtained by reading the watch-dog timer control register. If identifying the reset cause is requiredafter the reset is released, ensure that the value read from the watch-dog timer control register is processed by software and processing branches to an appropriate program. Figure 5.3-2 is a diagram of the watch-dog timer control register.
73
CHAPTER 5 CLOCK AND RESET Figure 5.3-1 Reset Cause bit Block Diagram
HSTX pin HSTX=L Power on Power-on detection circuit Hardware standby release detection circuit External reset request detection circuit Watch-dog timer reset detection circuit RSTX pin RSTX=L Without periodic clear RST bit set STBYC.RST bit write detection circuit
S Q
R
S Q
R
S Q
R
S
R
S
R Delay circuit
F/F
F/F
F/F
F/F
Q
F/F
Q
WTC register
WTC register read
F2MC-16L internal bus
Figure 5.3-2 WDTC (Watch-Dog Timer Control) Register
7 Address: 0000A8 H Read/write Initial value
6
5
4 ERST (R) (X)
3 SRST (R) (X)
2 WTE (W) (X)
1 WT1 (W) (X)
0 WT0 (W) (X)
Bit No. WDTC
PONR STBR WRST (R) (X) (R) (X) (R) (X)
When there are multiple reset causes, the corresponding reset cause bits in the watch-dog timer control register are set. Therefore, if an external reset request and a watch-dog reset occur at the same time, both the ERST and WRST bits are set to 1. A power-on reset is an exception; while the PONR bit is 1, the values of other bits do not indicate the correct reset causes. Therefore, design software so that the other reset cause bit values are ignored while the PONR bit is set to 1. Table 5.3-2 Reset Cause Bits Reset cause Power-on Hardware standby Watch-dog timer External pin RST bit PONR 1 * * * * STBR 1 * * * WRST * 1 * * ERST * * 1 * SRST * * * 1
(An asterisk (*) in the table means that the previous value is maintained.)
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CHAPTER 6
LOW-POWER CONTORL CIRCUIT
This chapter explains the functions and operations of the low-power control circuits. 6.1 Outline of Low-Power Control Circuit 6.2 Registers 6.3 Low-Power Mode Operation 6.4 Intermittent CPU Operation 6.5 Switching Machine Clocks 6.6 Status Transition of Clock Selection
75
CHAPTER 6 LOW-POWER CONTORL CIRCUIT
6.1
Outline of Low-Power Control Circuit
The MB90590 Series supports various operation modes to help reduce the power dissipation. The operation modes include PLL clock mode, PLL sleep mode, timer mode, main clock mode, main sleep mode, stop mode, and hardware standby mode. Modes other than PLL clock mode are classified as low-power modes.
s Outline of Lower-power Control Circuit In main clock mode or main sleep mode, the main clock (OSC oscillation clock) is used. The operation clock is generated by dividing the main clock by two, and the PLL clock (VCO oscillation clock) is stopped. In PLL sleep mode or main sleep mode, only the CPU operation clock is stopped. All other clocks are in operation. In timer mode, only the time base timer is in operation.In stop mode or hardware standby mode, oscillation is stopped. The data can be maintained at the lowest power consumption possible. The intermittent CPU operation function is used to intermittently enable the clock supplied to the CPU when a register, internal memory, internal resource, or external bus is accessed. CPU execution is slowed while high-speed clock is supplied to the internal resources, enabling processing at low power consumption. The PLL clock multiplication factor can be selected from 1, 2, 3, and 4 by setting the CS1 and CS0 bits. The oscillation stabilization wait time for the main clock upon release of stop or hardware standby mode can be set by the WS1 and WS0 bits.
76
6.1 Outline of Low-Power Control Circuit s Block Diagram Figure 6.1-1 Low-power Control Circuit and Clock Generator
CKSCR MCM MCS CKSCR CS1 CS0 CPU clock selector 0/9/17/33 intermittent cycle selection PLL multiplication circuit Main clock (OSC oscillation) 1/2 CPU clock generation CPU clock
1
2
3
4
F2MC-16 bus
LPMCR CG1 CG0 Intermittent CPU operation function Cycle count selection circuit Peripheral clock generation Standby control circuit HST RST Release activation HSTX pin Interrupt request or RST CKSCR OSC1 OSC0 LPMCR SPL Pin high-impedance control circuit Pin HI-Z Oscillation stabilization wait time selector
LPMCR SLP STP
Peripheral clock
210 213 215 217*
Clock input Time base timer 212 214 216 219
Time base clock
LPMCR RST
Internal reset generation circuit
RSTX pin Internal RST
To watch-dog
timer
WDGRST
*:
218
at power-on
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CHAPTER 6 LOW-POWER CONTORL CIRCUIT
6.2
Registers
A low-power control circuit has the following two registers: * Low-power mode control register (LPMCR) * Clock selection register (CKSCR)
s Low Power Mode Control Register
Address: 0000A0H Read/write Initial value
7
STP
6
SLP
5
SPL
4
RST
3
Reserved
2
CG1
1
CG0
0
Reserved
Bit No.
LPMCR
(W) (0)
(W) (0)
(R/W) (0)
(W) (1)
(-) (1)
(R/W) (0)
(R/W) (0)
(-) (0)
Clock selection register
Address: 0000A1H Read/write Initial value
15
Reserved
14
MCM
13
WS1
12
WS0
11
Reserved
10
MCS
9
CS1
8
CS0
Bit No.
CKSCR
(-) (1)
(R) (1)
(R/W) (1)
(R/W) (1)
(-) (1)
(R/W) (1)
(R/W) (0)
(R/W) (0)
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6.2 Registers
6.2.1
Low Power Mode Control Register (LPMCR)
In association with the clock selection register, the low-power mode control register sets various operation modes to reduce power consumption.
s Low Power Mode Control Register (LPMCR)
Address: 0000A0 H Read/write Initial value
7
STP (W) (0)
6
SLP (W) (0)
5
SPL (R/W) (0)
4
RST (W) (1)
3
Reserved (-) (1)
2
CG1 (R/W) (0)
1
CG0 (R/W) (0)
0
Bit No.
Reserved LPMCR (-) (0)
[bit 7] STP Writing '1' to this bit starts the timer mode (CKSCR.MCS=0) or stop mode (CKSCR.MCS=1). Writing '0' performs no operation. This bit is cleared to '0' upon a reset, timer mode release, or stop mode release. This is a write-only bit. '0' is always read from this bit. [bit 6] SLP Writing '1' to this bit starts sleep mode. Writing '0' performs no operation. This bit is cleared to '0' upon a reset, clock release, or stop release. Writing '1' to the STP and SLP bits simultaneously starts clock or stop mode. This is a writeonly bit. '0' is always read from this bit. [bit 5] SPL When '0' is written to this bit, the external pin level in timer mode or stop mode is maintained. When '1' is written to this bit, the external pin in clock or stop mode is set to high impedance. This bit is cleared to '0' upon a reset. This bit is readable and writable. It is important to note that when SPL is set to 0 and the microcontroller is in the stop mode (STP=1 and MCS=1), all inputs must be provided with stable digital values. Otherwise it results in current consumption at the input buffers. (A/D analog inputs are exception) Generally it is recommended to set the SPL bit to 1 when the microcontroller is in the stop mode inorder to disable all input buffers. [bit 4] RST Writing '0' to this bit generates internal reset signals for three machine cycles. Writing '1' performs no operation. '1' is always read from this bit. [bits 2 and 1] CG1 and CG0 These bits are used to set the clock pause cycle count during intermittent CPU operation. These bits are initialized to '00' upon a reset by power-on, hardware standby, or watch-dog. These bits are not initialized by any other type of reset. These bits are readable and writable. The intermittent CPU operation function pauses the clock to the CPU when a register, internal memory, internal resource, or external bus is accessed, thus delaying the activation of the internal bus cycle. CPU execution is slowed while high-speed clock is supplied to an
79
CHAPTER 6 LOW-POWER CONTORL CIRCUIT internal resource, enabling processing at low power consumption. Table 6.2-1 CG Bit Setting CG1 0 0 1 1 CG0 0 1 0 1 CPU clock pause cycle count 0 cycle (CPU clock = Resource clock) 9 cycles (CPU clock: Resource clock = 1:3 to 4 approx.) 17 cycles (CPU clock: Resource clock = 1:5 to 6 approx.) 33 cycles (CPU clock: Resource clock = 1:9 to 10 approx.)
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6.2 Registers
6.2.2
Clock Selection Register (CKSCR)
The clock selection register sets and controls the CPU machine clock, and sets the oscillation stabilization wait time when power is turned on or oscillation is restored.
s Clock Selection Register (CKSCR)
Address: 0000A1 H Read/write Initial value
15 Reserved (-) (1)
14 MCM (R) (1)
13 WS1 (R/W) (1)
12 WS0 (R/W) (1)
11 Reserved (-) (1)
10 MCS (R/W) (1)
9 CS1 (R/W) (0)
8 CS0 (R/W) (0)
Bit No. CKSCR
[bit 14] MCM This bit indicates whether the main clock or PLL clock is selected as the machine clock. '0' indicates that the PLL clock is selected, and '1' indicates that the main clock is selected. When MCS=0 and MCM=1, the system is waiting for the PLL clock oscillation to stabilize. The PLL clock oscillation stabilization wait time is fixed to 213 main clock cycles. [bits 13 and 12] WS1 and WS0 These bits are used to set the main clock oscillation stabilization wait time upon release of stop or hardware standby mode. These bits are initialized to '11' upon a power-on reset. These bits are not initialized by any other type of reset. These bits are readable and writable. Table 6.2-2 WS Bit Setting WS1 0 0 1 1 WS0 0 1 0 1 Oscillation stabilization wait time (at 4 MHz source oscillation) Approx. 256s (210 counts of source oscillation) Approx. 2.05 ms (213 counts of source oscillation) Approx. 8.19 ms (215 counts of source oscillation) Approx. 32.77 ms (217 counts of source oscillation)
*: Approx. 65.54ms (218 counts of source oscillation) at power-on. More stabilization time of 217 is added to the default duration only upon with the power-on reset. Therefor, after power-on there will be about 65.54ms of the stabilization time. [bit 10] MCS This bit is used to select the main clock or PLL clock as the machine clock. Writing '0' selects the PLL clock and writing '1' selects the main clock. When this bit is updated from '1' to '0,' the PLL clock oscillation stabilization wait period is created by automatically clearing the time base timer and the TBOF bit of the time base timer control register. The oscillation stabilization wait time for the PLL clock is fixed to 213 main clock cycles. (The oscillation wait time is about 2 ms at 4 MHz source oscillation.)
81
CHAPTER 6 LOW-POWER CONTORL CIRCUIT When the main clock is selected, the operation clock is generated by dividing the main clock by two. (The operation clock is 2 MHz at 4 MHz source oscillation.) This bit is initialized to '1' by the power-on reset, hardware standby, or watch-dog reset. But it is not initialized by the external reset from the RSTX pin or by the software reset (the RST bit in the LPMCR register). Note: When updating the MCS bit from '1' to '0,' ensure that the time base timer interrupt is masked by the TBIE bit or the ILM bit of the CPU. [bits 9 and 8] CS1 and CS0 These bits are used to select the multiplication factor of the PLL clock. These bits are initialized to '00' upon a power-on reset. These bits are not initialized by any other type of reset. Write is disabled when '0' is written to the MCS bit. To update the CS bit, set '1' in the MCS bit (to start main clock mode). These bits are readable and writable. Table 6.2-3 CS Bit Setting CS1 0 0 1 1 Note: When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz and 16 MHz. Since the highest operating frequency for the CPU and peripheral resource circuits is 16 MHz, however, normal operation is not guaranteed if a multiplication factor resulting in a higher frequency than 16 MHz is specified. For example, if the source oscillation is 16 MHz, only 1 can be specified as the multiplication factor. The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation below 4 MHz must not be specified. CS0 0 1 0 1 Machine clock (at 4 MHz source oscillation) 4 MHz (Operation frequency = OSC oscillation frequency) 8 MHz (Operation frequency = OSC oscillation frequency *2) 12 MHz (Operation frequency = OSC oscillation frequency *3) 16 MHz (Operation frequency = OSC oscillation frequency *4)
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6.3 Low-Power Mode Operation
6.3
Low-Power Mode Operation
Table 6.3-1 lists the chip status in each operation mode.
s Low-power Mode Operation
Table 6.3-1 Low-power mode status
Transition condition Main sleep PLL sleep Timer (SPL=0) Timer (SPL=1) Stop (SPL=0) Stop (SPL=1) Hardwar e standby MCS=1 SLP=1 MCS=0 SLP=1 MCS=0 STP=1 MCS=0 STP=1 MCS=1 STP=1 MCS=1 STP=1 HSTX=L Oscillation & T.B.T Operating Operating Operating Operating Stopped PLL Regulator CPU Watch Timer Operating Operating Operating Operating Stopped Other Peripheral Operating Operating Stopped Pin Release method Reset Interrupt Reset Interrupt Reset Interrupt Reset Interrupt Reset Interrupt Reset Interrupt HSTX= H
Stopped
Operating Operating Operating Operating Stopped
Stopped
Operating Operating Held
Operating Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
HI-Z
Stopped
Stopped
Stopped
Held*
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
HI-Z
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
HI-Z
Note: When the SPL is set to 0 in the stop mode, all inputs must be provided with stable digital values. Otherwise it results in current consumption at the input buffers. (A/D analog inputs are exception)
83
CHAPTER 6 LOW-POWER CONTORL CIRCUIT s Note: Low-power Mode Control Register Access Writing data to the low-power mode control register starts low-power mode (stop or sleep mode). In this case, use an instruction shown in Table 6.3-2. If any other instruction is used to start low-power mode, misoperation may result. Any instruction can be used to control functions other than transition of the low-power mode control register to low-power mode. To write data to the low-power mode control register in word length, ensure that the data is written to an even-number address. If low-power mode is started by writing data to an oddnumber address, misoperation may result. Table 6.3-2 List of Instructions Used for Transition to Low-power Mode MOV io,#imm8 MOV io,A MOV RLi+dip8,A MOVW io,#imm16 MOVW io,A MOVW RLi+dip8,A SETB io:bp MOV dir,#imm8 MOV dir,A MOVP addr24,A MOVW dir,#imm16 MOVW dir,A MOPW addr24,A SETB dir:bp MOV eam,#imm8 MOV addr16,A MOVW eam,#imm16 MOVW addr16,A SETB addr16:bp MOV eam,#immRi MOV eam,A MOVW eam,RWi MOVW eam,A
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6.3 Low-Power Mode Operation
6.3.1
Sleep Mode
In sleep mode, only the clock supplied to the CPU is stopped. As a result, the CPU terminates while peripheral circuits keep operating.
s Transition to Sleep Mode The standby control circuit is set in sleep mode by writing '1' to the SLP bit and '0' to the STP bit of the low power mode control register. In sleep mode, only the clock supplied to the CPU is stopped. The CPU stops, and the peripheral circuits continue operation. If an interrupt request has been issued when '1' is written to the SLP bit, the standby control circuit does not enter sleep mode. Therefore, the CPU executes the next instruction if the interrupt cannot be accepted, or immediately branches to the interrupt processing routine if the interrupt can be accepted. In sleep mode, the values of special registers such as the accumulator and the internal RAM are maintained. The external bus hold function works even in sleep mode. If there is a hold request, the hold status is entered. s Releasing Sleep Mode The standby control circuit releases sleep mode in the event of a reset input or an interrupt. If sleep mode is released by a reset, the reset status takes effect after sleep mode is released. If a peripheral circuit or similar issues an interrupt request of a higher interrupt level than 7 in sleep mode, the standby control circuit releases sleep mode. After sleep mode is released, processing is handled as normal interrupt processing. The CPU executes interrupt processing if the interrupt can be accepted according to the I flag, ILM, and the interrupt control register (ICR). If the interrupt cannot be accepted, processing continues from the instruction following the instruction that was being executed before the transition to sleep mode. Note: Usually, interrupt processing is started after the instruction following the instruction that was executed during the transition to sleep mode. If, however, transition to sleep mode and acceptance of the external bus hold request are simultaneous, interrupt processing may start before the next instruction is executed.
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CHAPTER 6 LOW-POWER CONTORL CIRCUIT
6.3.2
Timer Mode
Timer mode stops operations other than the source oscillation, time base timer, and watch-dog timer, resulting in almost all functions of the chip being stopped.
s Transition to Timer Mode The standby control circuit is set to timer mode when the MCS bit of the clock selection register is '0' and '1' is written to the STP bit of the low-power mode control register. In timer mode, all operations are stopped except for the source oscillation and time base timer. Most functions of the chip stop. Using the SPL bit of the low-power mode control register, the I/O pin may be maintained at the immediately preceding status or at high impedance in timer mode. If an interrupt request has been issued when '1' is written to the STP bit, the standby control circuit does not enter timer mode. In timer mode, the values of special registers such as the accumulator and the internal RAM are maintained. The external bus hold function is disabled in timer mode. No hold request is accepted. If a hold request is input during transition to timer mode, the HAKX signal may not become 'L' while the bus is Hi-Z. s Releasing Timer Mode The standby control circuit releases timer mode in the event of a reset input or an interrupt. If timer mode is released by a reset, the reset status takes effect after timer mode is released. To return from timer mode, the standby control circuit initially releases timer mode, then enters the PLL clock oscillation stabilization wait state. The MCS bit is not cleared by an external reset, so the reset sequence is performed using the main clock if the reset period is shorter than the PLL clock oscillation stabilization wait period. The PLL clock oscillation stabilization wait period is 213 to 3*213 main clock cycles depending on the time base timer status, because the time base timer is not cleared. If a peripheral circuit or similar issues an interrupt request of a higher interrupt level than 7 in timer mode, the standby control circuit releases timer mode. After the timer mode is released, processing is handled as normal interrupt processing. The CPU executes interrupt processing if the interrupt can be accepted according to the I flag, ILM, and the interrupt control register (ICR). If the interrupt cannot be accepted, processing continues from the instruction following the instruction that was being executed during transition to timer mode. Note: Usually, interrupt processing is started after the instruction following the instruction that was being executed during the transition to timer mode. If, however, transition to timer mode and acceptance of the external bus hold request are simultaneous, interrupt processing may start before the next instruction is executed. The standby control circuit enters PLL clock oscillation stabilization wait status when timer mode is released. If the PLL clock is not used, write '1' to the MCS bit by an instruction immediately following the reset or interrupt.
86
6.3 Low-Power Mode Operation
6.3.3
Stop Mode
Stop mode stops the source oscillation, resulting in all functions of the chip being stopped. Data can be maintained at the lowest power consumption possible.
s Transition to Stop Mode The standby control circuit is set to stop mode when the MCS bit of the clock selection register is '1' and '1' is written to the STP bit of the low-power mode control register. In stop mode, the source oscillation is stopped and all functions of the chip are stopped. Therefore, data can be maintained at the lowest power consumption possible. Using the SPL bit of the LPMCR, the I/O pins can be maintained at the immediately preceding status or at high impedance in stop mode. When the SPL bit is set to 0, all inputs must be provided with stable digital values. Otherwise it results in current consumption at the input buffers. (A/D analog inputs are exception) If an interrupt request has been issued when '1' is written to the STP bit, the standby control circuit does not enter the stop mode. In stop mode, the values of special registers such as the accumulator and the internal RAM are maintained. The external bus hold function is disabled in stop mode. No hold request is accepted. If a hold request is input during the transition to stop mode, the HAKX signal may not become 'L' while the bus is Hi-Z. s Releasing Stop Mode The standby control circuit releases stop mode in the event of a reset input or an interrupt. If stop mode is released by a reset, the reset status takes effect after stop mode is released. To return from stop mode, the standby control circuit initially enters the PLL clock oscillation stabilization wait status, and then releases stop mode. Even if stop mode is released by a reset, the reset sequence is executed after the oscillation stabilization wait period. If a peripheral circuit or similar issues an interrupt request of a higher interrupt level than 7 in stop mode, the standby control circuit releases stop mode. After stop mode is released, the processing is handled as normal interrupt processing after the main clock oscillation stabilization wait period specified by the WS1 and WS0 bits of CKSCR. The CPU executes interrupt processing if the interrupt can be accepted according to the I flag, ILM, and the interrupt control register (ICR). If the interrupt cannot be accepted, processing continues from the instruction following the instruction that was being executed during transition to stop mode. s Setting the Oscillation Stabilization Wait Time Use the WS1 and WS0 bits to specify the oscillation stabilization wait time when stop mode or hardware standby mode is released. Specify the oscillation stabilization wait time according to the types and characteristics of the oscillator circuit and oscillator device connected to the X0 and X1 pins. These bits are not initialized upon a reset, except for a power-on reset. Upon a power-on reset, these bits are initialized to '11.' Therefore, at power-on, the oscillation stabilization wait time is about 217 counts of source oscillation. Note: Usually, interrupt processing is started after the instruction following the instruction that was being executed during the transition to stop mode. If, however, transition to stop mode and
87
CHAPTER 6 LOW-POWER CONTORL CIRCUIT acceptance of the external bus hold request are simultaneous, interrupt processing may start before the next instruction is executed.
88
6.3 Low-Power Mode Operation
6.3.4
Hardware Standby Mode
In the hardware standby mode, oscillation is stopped and all I/O pins are set to high impedance while the HSTX pin is at "L" level, regardless of other statuses (including reset).
s Transition to Hardware Standby Mode The standby control circuit can be set in hardware standby mode from any status by setting the HSTX pin at 'L' level. In hardware standby mode, oscillation is stopped and all I/O pins are set to high impedance while the HSTX pin is at 'L' level, regardless of other status including reset. In hardware standby mode, the internal RAM contents are maintained but the special registers such as the accumulator are initialized. s Releasing Hardware Standby Mode Hardware standby mode can be released only by the HSTX pin. When the HSTX pin is set at 'H' level, the standby control circuit releases hardware standby mode, enables the internal reset signal, and enters oscillation stabilization wait status. After the oscillation stabilization wait period, the standby control circuit releases the internal reset, and consequently the CPU starts execution from the reset sequence. s Setting the Oscillation Stabilization Wait time Use the WS1 and WS0 bits to specify the oscillation stabilization wait time when stop mode or hardware standby mode is released. Specify the oscillation stabilization wait time according to the types and characteristics of the oscillator circuit and oscillator device connected to the X0 and X1 pins. These bits are not initialized upon a reset, except for a power-on reset. Upon a power-on reset, these bits are initialized to '11.' Therefore, at power-on, the oscillation stabilization wait time is about 217 counts of source oscillation.
89
CHAPTER 6 LOW-POWER CONTORL CIRCUIT
6.4
Intermittent CPU Operation
The intermittent CPU operation function pauses the clock supplied to the CPU when a register, internal memory (ROM, RAM, I/O, or resource), or external bus is accessed, delaying the activation of the internal bus cycle. The CPU execution speed is decreased while a high-speed clock is supplied to internal resources, thus enabling processing at low power consumption.
s Intermittent CPU Operation Figure 6.4-1 is a diagram of intermittent CPU operation. For intermittent CPU operation, the CG1 and CG0 bits are used to select the cycle count for clock pausing. The external bus operation itself is performed using the same clock as that used for the resources. An instruction execution time using the intermittent CPU operation function can be obtained by adding a compensation value to the ordinary execution time. The compensation value is obtained by multiplying the number of accesses to a register, internal memory, internal resource, or external bus by the cycle count for pausing. Figure 6.4-1 Intermittent CPU Operation
Peripheral clock CPU clock Intermittent operation pause cycle Internal bus activation cycle
90
6.5 Switching Machine Clocks
6.5
Switching Machine Clocks
Writing to the MCS bit in the CKSCR register switches the machine clock from the main clock to the PLL clock.
s Switching between Main Clock and PLL Clock Write data to the MCS bit of the CKSCR register to switch between the main clock and PLL clock. When the MCS bit is changed from '1' to '0,' the PLL clock takes over the main clock after the PLL clock oscillation stabilization wait time (213 machine clock cycles). When the MCS bit is changed from '0' to '1,' the main clock takes over the PLL clock when the edges of the PLL and main clocks match (after about 1 to 8 PLL clock cycles). Writing to the MCS bit does not change the machine clock immediately. To manipulate a resource that depends on the machine clock, always reference the MCM bit before hand to check that the machine clock has been switched. s Initializing the Machine Clock The MCS bit is not initialized by a reset using an external pin or RST bit. The MCS bit is initialized to '1' by any other reset.
91
CHAPTER 6 LOW-POWER CONTORL CIRCUIT
6.6
Status Transition of Clock Selection
The oscillation stabilization wait time for the PLL clock is fixed at 213 main clock cycles. (The oscillation wait time is about 2 ms at a source oscillation of 4 MHz.)
s Status Transition of Clock Selection Figure 6.6-1 is a diagram of status transition of clock selection. Figure 6.6-1 Status Transition of Clock Selection
Power on Main MCS = 1 MCM = 1 CS1/0=xx MainPLLx MCS = 0 MCM = 1 CS1/0=xx
PLLMain MCS = 1 MCM = 0 CS1/0=00

PLL1 multiplication MCS = 0 MCM = 0 CS1/0=00
PLL2 multiplication MCS = 0 MCM = 0 CS1/0=01
PLL2Main MCS = 1 MCM = 0 CS1/0=01 PLL3Main MCS = 1 MCM = 0 CS1/0=10
PLL3 multiplication MCS = 0 MCM = 0 CS1/0=10
PLL4Main MCS = 1 MCM = 0 CS1/0=11
PLL4 multiplication MCS = 0 MCM = 0 CS1/0=11
x y z { | } ~
MCS bit clear End of PLL clock oscillation stabilization wait & CS1/0=00 End of PLL clock oscillation stabilization wait & CS1/0=01 End of PLL clock oscillation stabilization wait & CS1/0=10 End of PLL clock oscillation stabilization wait & CS1/0=11 MCS bit set (including hardware standby and watch-dog reset) Synchronization timing between PLL clock and main clock
92
CHAPTER 7
MEMORY ACCESS MODES
This chapter explains the functions and operations of the memory access modes. 7.1 Outline of Memory Access Modes 7.2 Mode Pins 7.3 Mode Data
93
CHAPTER 7 MEMORY ACCESS MODES
7.1
Outline of Memory Access Modes
In the F2MC-16LX, the following three memory access modes are provided for each of the access methods, access areas, and tests: * Operation mode * Bus mode * Access mode
s Memory Access Modes
Operation mode
Bus mode Single chip Internal ROM, external bus External ROM, external bus
Access mode External data bus length 8 bits 16 bits
ORUN EPROM write Test functions
For the MB90590 Series, the external bus function is not supported. Therefor the following part of this document is not fully supported. In user applications, please use the MB90590 Series in the single chip mode. To set the MB90590 Series into the signle chip mode, the mode inputs (MD2 to 0) should be "011" and the most significant two bits of the mode data (M1 and M0) should be "00". r Operation mode Operation mode means the mode for controlling the device operation status. The operation mode is specified by the MDx mode setting pin and the Ex bit in mode data. By selecting an operation mode, normal operation, internal test program activation, or special test function activation can be performed. r Bus mode Bus mode means the mode for controlling the internal ROM operation and external access function. The bus mode is specified by the MDx mode setting pin and the Mx bit in mode data. The MDx mode setting pin specifies the bus mode for reading the reset vector and mode data, and the Mx bit in mode data specifies the bus mode for normal operation. r Access mode Access mode means the mode for controlling the external data bus width. The access mode is specified by the MDx mode setting pin and the SO bit in mode data. By selecting an access mode, an 8- or 16-bit external data bus is specified.
94
7.2 Mode Pins
7.2
Mode Pins
Table 7.2-1 describes the operations specified by combinations of the MD2 to MD0 external pins.
s Mode pins
Table 7.2-1 Mode Pins and Modes Mode pin setting MD2 MD1 MD0 0 0 0 0 0 1 0 1 0 Mode name External vector mode 0 External vector mode 1 External vector mode 2 Reset vector access area External External External External data bus width 8 bits 16 bits 16 bits Reset vector, 16-bit bus width access Reset vector, 8-bit bus width access Reset sequence and later segments are controlled based on mode data. Remarks
0
1
1
Internal vector mode
Internal
(Mode data)
1 1 1 1
0 0 1 1
0 1 0 1 Flash memory --Reserved
In External vector mode 2, the HMBS bit of the bus control signal selection register is set to '1,' and the bus width for external access to the area between 800000H and FFFFFFH is 8 bits. Use External vector mode 2 when the bus width for the ROM is 8 bits but the bus width for the RAM or other components is 16 bits. In External vector mode 1, the HMBS bit is set to '0' and the access bus width becomes 16 bits.
95
CHAPTER 7 MEMORY ACCESS MODES
7.3
Mode Data
Mode data is stored at FFFFDFH of main memory and used for controlling the CPU operation. This data is fetched during a reset sequence and stored in the mode register inside the device. The mode register value can be changed only by a reset sequence. The setting of this register is valid after the reset sequence. Always set the reserved bits to '0.'
s Mode Data Figure 7.3-1 is a diagram of the setting of the bits. Figure 7.3-1 Mode Data Structure
7 Mode data M1
6 M0
5 0
4 0
3 S0
2 0
1 0
0 0
Function extension bit (reserved area) Mode setting bits Bus mode setting bits
s Mode Setting BitsMode Setting Bits These bits are used to specify the bus mode or access mode after the reset sequence is completed. Table 7.3-1 shows the relationship between the bits and the functions. Table 7.3-1 Mode Setting Bits and Functions S0 0 1 s Bus Mode Setting Bits These bits are used to specify the operation mode after the reset sequence is completed. Table 7.3-2 shows the relationship between the bits and the functions. Table 7.3-2 Bus Mode Setting Bits and Functions M1 0 0 1 1 M0 0 1 0 1 Single chip mode Internal ROM and external bus mode External ROM and external bus mode (Inhibited) Function Remarks Function External data bus, 8-bit mode External data bus, 16-bit mode Remarks
96
7.3 Mode Data Figure 7.3-2 is a diagram of the correspondence between the access areas and physical addresses for each bus mode. Figure 7.3-2 Access Areas and Physical Addresses in each Bus Mode
FFFFFF H ROM Devicedependent #1 ROM
FF0000 H
010000 H ROM 004000 H ROM
Devicedependent
002100 H 001100 H
RAM I/O RAM
RAM I/O RAM
RAM I/O : No access RAM : Internal access : External access
000100 H 0000C0 H 000000 H
I/O Single chip
I/O Internal ROM, external bus
I/O External ROM, external bus
Note: "Device-dependent" means an address that is determined depending on the device. s Recommended Setting Table 7.3-3 lists a sample recommended setting of mode pins and mode data. Table 7.3-3 Sample Recommended Setting of Mode Pins and Mode Data Sample setting Single chip Internal ROM and external bus mode, 16-bit bus Internal ROM and external bus mode, 8-bit bus External ROM and external bus mode, 16-bit bus, vector 16 bus width External ROM and external bus mode, 16-bit bus, vector 8 bus width MD2 0 0 0 0 0 MD1 1 1 1 0 1 MD0 1 1 1 1 0 M1 0 0 0 1 1 M0 0 1 1 0 0 S0
x
1 0 1 1
97
CHAPTER 7 MEMORY ACCESS MODES Table 7.3-3 Sample Recommended Setting of Mode Pins and Mode Data (Continued) Sample setting External ROM and external bus mode, 8-bit bus MD2 0 MD1 0 MD0 0 M1 1 M0 0 S0 0
98
CHAPTER 8
I/O PORTS
This chapter explains the functions and operations of the I/O ports. 8.1 I/O Port 8.2 I/O Port Registers
99
CHAPTER 8 I/O PORTS
8.1
I/O Ports
Each pin of the ports can be specified as input or output using the direction register if the corresponding peripheral does not use the pin. When a pin is specified as input, the logic level at the pin is read. When a pin is specified as output, the data register value is read. The above also applies to a read operation for the read-modify-write instructions. Only for Port 0, Port 1, Port 2 and Port 3, the corresponding bits of the Port Direction registers should be set to "1" in oder to enable peripheral signal outputs.
s I/O Ports When a pin is used as an output of other peripheral function, the peripheral output value is read regardless of the direction register value. It is generally recommended that the read-modify-write instructions should not be used for setting the data register prior to setting the port as an output. This is because the read-modifywrite instruction in this case results reading the logic level at the port rather than the register value. Figure 8.1-1 is a block diagram of the I/O ports. Figure 8.1-1 I/O Port Block Diagram
Internal data bus
Data register read Data register Data register write Direction register Direction register write Pin
Direction register read
100
8.2 I/O Port Registers
8.2
I/O Port Registers
There are three types of I/O port registers: * Port data register (PDR0 to 9) * Port direction register (DDR0 to 9) * Analog input enable register (ADER)
s I/O Port Registers Figure 8.2-1 shows the I/O port registers. Figure 8.2-1 I/O Port Registers
Bit Address : 000000 H Address : 000001 H Address : 000002 H Address : 000003 H Address : 000004 H Address : 000005 H Address : 000006 H Address : 000007 H Address : 000008 H Address : 000009 H 15/7 P07 P17 P27 P37 P47 P57 P67 P77 P87 14/6 P06 P16 P26 P36 P46 P56 P66 P76 P86 13/5 P05 P15 P25 P35 P45 P55 P65 P75 P85 P95 12/4 P04 P14 P24 P34 P44 P54 P64 P74 P84 P94 11/3 P03 P13 P23 P33 P43 P53 P63 P73 P83 P93 10/2 P02 P12 P22 P32 P42 P52 P62 P72 P82 P92 9/1 P01 P11 P21 P31 P41 P51 P61 P71 P81 P91 8/0 P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 Port 0 data register (PDR0) Port 1 data register (PDR1) Port 2 data register (PDR2) Port 3 data register (PDR3) Port 4 data register (PDR4) Port 5 data register (PDR5) Port 6 data register (PDR6) Port 7 data register (PDR7) Port 8 data register (PDR8) Port 9 data register (PDR9)
Bit Address : 000010 H Address : 000011 H Address : 000012 H Address : 000013 H Address : 000014 H Address : 000015 H Address : 000016 H Address : 000017 H Address : 000018 H Address : 000019 H
15/7 D07 D17 D27 D37 D47 D57 D67 D77 D87
14/6 D06 D16 D26 D36 D46 D56 D66 D76 D86
13/5 D05 D15 D25 D35 D45 D55 D65 D75 D85 D95
12/4 D04 D14 D24 D34 D44 D54 D64 D74 D84 D94
11/3 D03 D13 D23 D33 D43 D53 D63 D73 D83 D93
10/2 D02 D12 D22 D32 D42 D52 D62 D72 D82 D92
9/1 D01 D11 D21 D31 D41 D51 D61 D71 D81 D91
8/0 D00 D10 D20 D30 D40 D50 D60 D70 D80 D90 Port 0 direction register (DDR0) Port 1 direction register (DDR1) Port 2 direction register (DDR2) Port 3 direction register (DDR3) Port 4 direction register (DDR4) Port 5 direction register (DDR5) Port 6 direction register (DDR6) Port 7 direction register (DDR7) Port 8 direction register (DDR8) Port 9 direction register (DDR9)
Bit Address : 00001B
15
14
13
12
11
10
9
8 Port 6 analog input enable register (ADER)
H ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
101
CHAPTER 8 I/O PORTS
8.2.1
Port Data Register
Note that R/W for I/O ports differ from R/W for memory in the following points: Input mode Read: The level at the corresponding pin is read. Write: Data is written to an output latch. Output mode Read: The data register latch value is read. Write: Data is written to an output latch and output to the corresponding pin.
s Port data Register Figure 8.2-2 shows the port data registers. Figure 8.2-2 Port Data Registers
7 PDR0 Address: 000000 H PDR1 Address: 000001 H P07 15 P17 7 PDR2 Address: 000002 H P27 15 PDR3 Address: 000003 H PDR4 Address: 000004 H P37 7 P47 15 PDR5 Address: 000005 H P57 7 PDR6 Address: 000006 H PDR7 Address: 000007 H P67 15 P77 7 PDR8 Address: 000008 H PDR9 Address: 000009 H P87 15 6 P06 14 P16 6 P26 14 P36 6 P46 14 P56 6 P66 14 P76 6 P86 14 5 P05 13 P15 5 P25 13 P35 5 P45 13 P55 5 P65 13 P75 5 P85 13 P95 4 P04 12 P14 4 P24 12 P34 4 P44 12 P54 4 P64 12 P74 4 P84 12 P94 3 P03 11 P13 3 P23 11 P33 3 P43 11 P53 3 P63 11 P73 3 P83 11 P93 2 P02 10 P12 2 P22 10 P32 2 P42 10 P52 2 P62 10 P72 2 P82 10 P92 1 P01 9 P11 1 P21 9 P31 1 P41 9 P51 1 P61 9 P71 1 P81 9 P91 0 P00 8 P10 0 P20 8 P30 0 P40 8 P50 0 P60 8 P70 0 P80 8 P90 Undefined R/W *1 Undefined R/W *1 Undefined R/W *1 Undefined R/W *1 Undefined R/W *1 Undefined R/W *1 Undefined R/W *1 Undefined R/W *1 Undefined R/W *1 Initial value Undefined Access R/W *1
102
8.2 I/O Port Registers
8.2.2
Port Direction Register
When a pin is used as a port, the corresponding pin is controlled as described below: 0: Input mode 1: Output mode
s Port Direction Register Figure 8.2-3 shows the port direction registers. Figure 8.2-3 Port Direction Registers
7 DDR0 Address: 000010 H D07 6 D06 5 D05 4 D04 3 D03 2 D02 1 D01 0 D00 Initial value 00000000 B Access R/W
15 DDR1 Address: 000011 H D17
14 D16
13 D15
12 D14
11 D13
10 D12
9 D11
8 D10 00000000 B R/W
7 DDR2 Address: 000012 H D27 15 DDR3 Address: 000013 H D37
6 D26 14 D36
5 D25 13 D35
4 D24 12 D34
3 D23 11 D33
2 D22 10 D32
1 D21 9 D31
0 D20 8 D30 00000000 B R/W 00000000 B R/W
7 DDR4 Address: 000014 H D47 15 DDR5 Address: 000015 H D57 7 DDR6 Address: 000016 H D67
6 D46 14 D56 6 D66
5 D45 13 D55 5 D65
4 D44 12 D54 4 D64
3 D43 11 D53 3 D63
2 D42 10 D52 2 D62 9
1 D41 8 D51 1 D61
0 D40 00000000 B R/W
D50 0 D60
00000000 B
R/W
00000000 B
R/W
15 DDR7 Address: 000017 H D77 7 DDR8 Address: 000018 H D87 15 DDR9 Address: 000019 H
14 D76 6 D86 14
13 D75 5 D85 13 D95
12 D74 4 D84 12 D94
11 D73 3 D83 11 D93
10 D72 2 D82 10 D92
9 D71 1 D81 9 D91
8 D70 0 D80 8 D90 __000000 B R/W 00000000 B R/W 00000000 B R/W
103
CHAPTER 8 I/O PORTS
8.2.3
Analog Input Enable Register
This register controls the port 6 pins as described below: 0: Port input/output mode 1: Analog input mode If an external pin is used as an analog input for the A/D converter, the corresponding bit should be set to "1".
s Analog Input Enable Register Figure 8.2-4 shows the analog input enable register. Figure 8.2-4 Analog Input Enable Register
bit Address: 00001B H 15 ADE7 R/W 14 ADE6 R/W 13 ADE5 R/W 12 ADE4 R/W 11 ADE3 R/W 10 ADE2 R/W 9 8 ADE1 R/W ADE0 R/W Initial value 11111111 B
104
CHAPTER 9 TIME BASE TIMER
This chapter explains the functions and operations of the time base timer. 9.1 Outline of Time Base Timer 9.2 Time Base Timer Control Register 9.3 Operations of Time Base Timer
105
CHAPTER 9 TIME BASE TIMER
9.1
Outline of Time Base Timer
The time base timer consists of an 18-bit time base counter and a control register. The 18-bit time base counter divides the system clock. The time base timer issues interrupts at specified intervals based on carry signals of the time base counter.
s Outline of Time Base Timer When the power is turned on, the time base counter can be cleared to all zeroes by setting the stop mode or by software (writing '0' to the TBR bit). The time base counter is incremented while the source oscillation is input. The time base counter can be used as a timer for supplying clock to the watch-dog timer or for waiting for the oscillation to stabilize. s Block Diagram of Time Base Timer Figure 9.1-1 shows a block diagram of the time base timer. Figure 9.1-1 Block Diagram of Time Base Timer
WTE WT1 WT0 Selector Two-bit counter Output enable Reset Reset control
Time base counter f/2 Power-on reset STOP mode TBR TBC1 TBC0
18 1/216 to 1/2
1 2 Clear control
1 2
11
1 2
12
1 2
13
1 2
14
1 2
15
1 2
16
1 2
17
1 218
TBOF Selector TBOF
IRQ
Clear EI 2OS Time base devision output
OSC1 OSC0 Selector
Osciliation stabilization wait completion signal
106
9.2 Time Base Timer Control Register
9.2
Time Base Timer Control Register
The time base timer control register controls interrupts of the time base timer and can clear the time base counter.
s Time Base Timer Control Register (TBTC)
15 bit TBTC Address: 0000A9 H Reserved W
[bit 15] Reserved
14
13
12 TBIE R/W
11 TBOF R/W
10 TBR W
9 TBC1 R/W
8 TBC0 R/W
Initial value 1- -00100 B
This is a reserved bit. When writing data to this register, ensure that '1' is written to this bit. [bit 12] TBIE This bit is used to enable interval interrupts based on the time base timer. Writing '1' to this bit enables interrupts, and writing '0' disables interrupts. This bit is initialized to '0' upon a reset. This bit is readable and writable. [bit 11] TBOF This is an interrupt request flag for the time base timer. While the TBIE bit is '1,' an interrupt request is issued when '1' is written to TBOF. This bit is set to '1' for each interval specified with the TBC1 and TBC0 bits. This bit is cleared by writing '0,' transition to stop or hardware standby mode, or a reset. Writing '1' has no effect. '1' is always read by a read-modify-write instruction. [bit 10] TBR This bit clears all bits of the time base timer counter to '0.' Writing '0' clears the time base counter. Writing '1' has no effect. '1' is always read from this bit. [bits 9 and 8] TBC1 and TBC0 These bits are used to set the time base timer interval. Table 9.2-1 lists the specifiable intervals. Table 9.2-1 Selecting the Time Base Timer Interval TBC1 0 0 TBC0 0 1 Interval at 4 MHz source oscillation 1.024 ms 4.096 ms
107
CHAPTER 9 TIME BASE TIMER Table 9.2-1 Selecting the Time Base Timer Interval (Continued) TBC1 1 1 TBC0 0 1 Interval at 4 MHz source oscillation 16.384 ms 131.072 ms
108
9.3 Operations of Time Base Timer
9.3
Operations of Time Base Timer
The time base timer functions as a watch-dog timer clock source, timer for waiting for the oscillation to stabilize, and interval timer for generating interrupts at specified intervals.
s Time Base Counter The time base counter consists of an 18-bit counter for a clock generated by dividing the source oscillation input by two. This clock is used to generate the machine clock. While the source oscillation is input, the time base counter keeps counting. The time base counter is cleared by a power-on reset, transition to stop or hardware standby mode, or writing '0' to the TBR bit of the TBTC register. s Interval Interrupt Function Interrupts are generated at specified intervals according to the carry signals of the time base counter. The TBOF flag is set at the intervals specified with the TBC1 and TBC0 bits of the TWC register. The flag is written to reference to the time at which the time base timer is cleared last. Upon transition to stop or hardware standby mode, the time base timer is used as a timer for waiting for the oscillation to stabilize upon recovery. Therefore, the TBOF flag is immediately cleared upon mode transition.
109
CHAPTER 9 TIME BASE TIMER
110
CHAPTER 10
WATCH-DOG TIMER
This chapter explains the functions and operations of the watch-dog timer. 10.1 Outline of Watch-Dog Timer 10.2 Watch-dog Timer Operations
111
CHAPTER 10 WATCH-DOG TIMER
10.1 Outline of Watch-Dog Timer
The watch-dog timer consists of a two-bit watch-dog counter, control register, and watch-dog reset controller. The two-bit watch-dog counter uses the carry signals of an 18-bit time base counter as a clock source.
s Watch-dog Timer Block Diagram Figure 10.1-1 is a diagram of the configuration of the watch-dog timer. Figure 10.1-1 Watch-dog Timer Block Diagram
WTE WT1 WT0 Selector Two-bit counter Output enable Reset Reset control
Time base counter f/2 Power-on reset STOP mode TBR TBC1 TBC0
18 1/216 to 1/2
1 2 Clear control
1 2
11
1 2
12
1 2
13
1 2
14
1 2
15
1 2
16
1 2
17
1 218
TBOF Selector TBOF
IRQ
Clear EI 2OS Time base devision output
OSC1 OSC0 Selector
Osciliation stabilization wait completion signal
112
10.1 Outline of Watch-Dog Timer s Watch-dog Timer Control Register (WDTC)
Bit
7
6
5
4
3
2 WTE W
1 WT1 W
0 WT0 W
Initial value XXXXX111 H
WDTC PONR STBR WRST ERST SRST Address : 0000A8H R R R R R
[bits 7 to 3] PONR, STBR, WRST, ERST, and SRST These flags indicate the reset causes. The flags are set upon a reset as described in Table 10.1-1. All bits are cleared to '0' after the WDTC register is read. These bits are read-only bits. For details, see Section 5.2 "Reset". Table 10.1-1 Reset Cause Registers Reset cause Power-on Hardware standby Watch-dog timer External pin RST bit PONR 1 * * * * STBR 1 * * * WRST * 1 * * ERST * * 1 * SRST * * * 1
(*: The previous value is maintained.) [bit 2] WTE While the watch-dog timer is stopped, writing '0' to this bit activates the watch-dog timer. Subsequently, writing '0' clears the watch-dog timer counter. Writing '1' has no effect. The watch-dog timer is stopped by power-on, hardware standby, or reset by watch-dog timer. '1' is always read from this bit. [bits 1 and 0] WT1 and WT0 These bits are used to select the watch-dog timer interval. Only the data items written during watch-dog timer activation are valid. Data items that are written outside watch-dog timer activation are ignored. Table 10.1-2 lists the interval settings. These bits are write-only bits. Table 10.1-2 Watch-dog Timer Interval Selection Bit Interval (at a source oscillation of 4 MHz) Minimum 0 0 1 0 1 0 approx. 3.58 ms approx. 14.33 ms approx. 57.23 ms Maximum approx. 4.61 ms approx. 18.43 ms approx. 73.73 ms 214 plus or minus 211 cycles 216 plus or minus 213 cycles 218 plus or minus 215 cycles Main clock cycle count
WT1
WT0
113
CHAPTER 10 WATCH-DOG TIMER Table 10.1-2 Watch-dog Timer Interval Selection Bit (Continued) Interval (at a source oscillation of 4 MHz) Minimum 1 1 approx. 458.7 ms Maximum approx. 589.82 ms 221 plus or minus 218 cycles Main clock cycle count
WT1
WT0
Note: The interval becomes the maximum when the time base counter is not reset during watch-dog timer operation.
114
10.2 Watch-dog Timer Operation
10.2 Watch-dog Timer Operation
The watch-dog timer function enables detection of program surge. If the watch-dog timer is not accessed within the specified time due to, for example, a program surge, the watch-dog timer resets the system.
s Activation The watch-dog timer is activated by writing '0' to the WTE bit of the WDTC register while the watch-dog timer is stopped. At the same time, the WT1 and WT0 bits are used to set the watchdog timer reset interval. Only the interval setting specified during activation is valid. s Watch-dog Counter Once the watch-dog timer is activated, the watch-dog timer counter must be periodically cleared within the program. Writing '0' to the WTE bit of the WDTC register clears the watch-dog counter. The watch-dog counter consists of a two-bit counter which uses the carry signals of the time base counter as a clock source. Therefore, the watch-dog reset time may become shorter than the setting if the time base counter is cleared. The watch-dog counter is cleared not only by writing to the WTE bit but also by a reset, transition to the sleep or stop mode, and a hold acknowledge signal. (The watch-dog counter is not cleared by transition to timer mode.) Figure 10.2-1 is a diagram of the watch-dog timer operation. Figure 10.2-1 Watch-dog Timer Operation
Time base Watch-dog WTE write Watch-dog activation Watch-dog clear Watch-dog reset 00 01 10 00 01 10 11 00
s Watch-dog Stop Once activated, the watch-dog timer is initialized and stopped only by power-on, hardware standby, or reset by watch-dog. Reset by an external pin or software merely clears the watchdog counter without stopping the watch-dog function.
115
CHAPTER 10 WATCH-DOG TIMER
116
CHAPTER 11
16-BIT I/O TIMER
This chapter explains the functions and operations of the 16-bit I/O timer. 11.1 Outline of 16-Bit I/O Timer 11.2 16-Bit I/O Timer Registers 11.3 16-bit Free-running Timer 11.4 Output Compare 11.5 Input Capture
117
CHAPTER 11 16-BIT I/O TIMER
11.1 Outline of 16-Bit I/O Timer
The MB90590 Series contains one 16-bit free-running timer module, three output compare modules, and three input capture modules and supports six input channels and six output channels. The following sections only describes the 16-bit free-running timer, Output Compare 0/1 and Input Capture 0/1. The remaining modules have the identical functions and the register addresses should be found in the I/O map.
s 16-bit Free-running Timer The 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. The values output from this timer counter are used as the base timer for input capture and output compare. r Four counter clocks are available. Internal clock:/4, /16, /64, /256 r An interrupt can be generated upon a counter overflow or a match with compare register 0. r The counter value can be initialized to '0000H' upon a reset, software clear, or match with compare register 0. s Output Compare (2 Channels per One Module) The output compare module consists of two 16-bit compare registers, compare output latch, and control register. When the 16-bit free-running timer value matches the compare register value, the output level is reversed and an interrupt is issued. r The two compare registers can be used independently. Output pins and interrupt flags corresponding to compare registers r Output pins can be controlled based on pairs of the two compare registers. Output pins can be reversed by using the two compare registers. r Initial values for output pins can be set. r Interrupts can be generated upon a compare match. s Input Capture (2 Channels per one Module) The input capture module consists of two 16-bit capture registers and control registers corresponding to two independent external input pins. The 16-bit free-running timer value can be stored in the capture register and an interrupt is issued simultaneously upon detection of an edge of a signal input from an external input pin.
118
11.1 Outline of 16-Bit I/O Timer r The detection edge of an external input signal can be specified. Rising, falling, or both edges r Two input channels can operate independently. r An interrupt can be issued upon a valid edge of an external input signal. The intelligent I/O service can be activated upon an input capture interrupt. s Block Diagram of 16-bit I/O Timer Figure 11.1-1 shows a block diagram of the 16-bit I/O timer. Figure 11.1-1 Block Diagram of 16-bit I/O Timer
Control logic To each block Clear Bus Output compare 0 Compare register 0 Output compare 1 Compare register 1 T Q OUT1 T Q OUT0 Interrupt 16-bit free-run timer 16-bit timer
Input capture 0 Capture register 0 Input capture 1 Capture register 1 Edge selection IN1 Edge selection IN0
119
CHAPTER 11 16-BIT I/O TIMER
11.2 16-Bit I/O Timer Registers
The 16-bit I/O timer has the following three registers: * 16-bit free-running timer register * 16-bit output compare register * 16-bit input capture register
s 16-bit Free-runningTimer
15 001944H 00006EH TCDT TCCS
0 Timer data register
Timer status register
s 16-bit Output Compare
15 001930H 001932H 000058H OCS1 OCCP0/1 OCS0
0 Compare register
Control status register
s 16-bit Input Capture
15 001920H 001922H 000054H IPCP0/1 ICS0/1
0 Capture register
Control status register
120
11.3 16-bit Free-running Timer
11.3 16-bit Free-running Timer
The 16-bit free-running timer consists of a 16-bit up counter and a control status register. The count values of this timer are used as the base timer for the output compares and input captures. * Four counter clock frequencies are available. * An interrupt can be generated upon a counter value overflow. * The counter value can be initialized upon a match with compare register 0, depending on the mode.
s 16-bit Free-running Timer Block Diagram
Figure 11.3-1 16-bit Free-running Timer Block Diagram
Interrupt request IVF IVFE STOP MODE CLR CLK1 CLK0 Comparator 0 Bus 16-bit up counter Clock Count value output T15 to T00 Divider
121
CHAPTER 11 16-BIT I/O TIMER
11.3.1 Data Register
The data register can read the count value of the 16-bit free-running timer. The counter value is cleared to '0000' upon a reset. The timer value can be set by writing a value to this register. However, ensure that the value is written while the operation is stopped (STOP=1). The data register must be accessed by the word access instructions.
s Data Register
bit
Address: 001945H
15 T15 R/W 0
14 T14 R/W 0 bit 7
13 T13 R/W 0
12 T12 R/W 0 6 T06 R/W 0 5
11 T11 R/W 0
10 T10 R/W 0 4 T04 R/W 0 3
9 T09 R/W 0
8 T08 Attribute R/W Initial value 0 2 T02 R/W 0 1 T01 R/W 0 0 T00 Attribute R/W Initial value 0
Address: 001944H
T07 R/W 0
T05 R/W 0
T03 R/W 0
The 16-bit free-running timer is initialized upon the following factors: * * * Reset Clear bit (CLR) of control status register A match between compare register 0 and the timer counter value.
122
11.3 16-bit Free-running Timer
11.3.2 Control Status Register
The control status register sets the operation mode of the 16-bit free-running timer, starts and stops the 16-bit free-running timer, and controls interrupts.
s Control Status Rgister
bit
7
6 IVF R/W 0
5 IVFE R/W 0
4 STOP R/W 0
3 MODE R/W 0
2 CLR R/W 0
1 CLK1 R/W 0
0 CLK0 R/W 0 Attribute Initial value
Address: 00006EH Reserved R/W 0
[bit 7] Reserved bit Always write '0' to this bit. [bit 6] IVF This bit is an interrupt request flag of the 16-bit free-running timer. If the 16-bit free-running timer overflows, or if the counter is cleared by a match with compare register 0, '1' is set to this bit. An interrupt is issued if the interrupt request enable bit (bit 5: IVFE) is set. This bit is cleared by writing '0.' Writing '1' has no effect. '1' is always read by a read-modify-write instruction. 0 1 [bit 5] IVFE IVFE is an interrupt enable bit of the 16-bit free-run timer. While this bit is "1", an interrupt is issued if '1' is set to the interrupt flag (bit 5: IVF). 0 1 [bit 4] STOP The STOP bit is used to stop the 16-bit free-running timer. Writing '1' to this bit stops the timer. Writing '0' starts the timer. 0 1 Counter enabled (operation) (initial value) Counter disabled (stop) Interrupt disabled (initial value) Interrupt enabled No interrupt request (initial value) Interrupt request
123
CHAPTER 11 16-BIT I/O TIMER Note: The output compare operation stops when the 16-bit free-running timer stops. [bit 3] MODE The MODE bit is used to set the reset condition of the 16-bit free-running timer. When '0' is set, the counter value can be initialized by RESET or a clear bit (bit 2: CLR). When '1' is set, the counter value can be initialized by a match with compare register 0 in addition to RESET and a clear bit (bit 2: CLR). 0 1 Note: The clear bit and the match with compare register initializes the timer when the timer value changes. [bit 2] CLR The CLR bit initializes the operating 16-bit free-running timer value to '0000.' When '1' is set, the counter value is initialized to '0000.' Writing '0' has no effect. '0' is always read from this bit. The counter value is initialized when the count value changes. 0 1 Note: To initialize the counter value while the timer is stopped, write '0000' to the data register. [bits 1 and 0] CLK1 and CLK0 CLK1 and CLK0 are used to select the count clock for the 16-bit free-run timer. The clock is updated immediately after a value is written to these bits. Therefore, ensure that the output compare and input capture operations are stopped before a value is written to these bits. CLK1 0 0 1 1 CLK0 0 1 0 1 Count clock /4 /16 /64 /256 =16 MHz 0.25 s 1 s 4 s 16 s =8 MHz 0.5 s 2 s 8 s 32 s =4 MHz 1 s 4 s 16 s 64 s =1 MHz 4 s 16 s 32 s 128 s No effect (initial value) The counter value is initialized to '0000.' Initialization by reset or clear bit (initial value) Initialization by reset, clear bit, or compare register 0
= Machine clock
124
11.3 16-bit Free-running Timer
11.3.3 16-bit Free-running TimerOperation
The 16-bit free-running timer starts counting from counter value '0000' after the reset is released. The counter value is used as the reference time for the 16-bit output compare and 16-bit input capture operations.
s 16-bit Free-running Timer Operation The counter value is cleared in the following conditions: * * * * * When an overflow occurs. When a match with the output compare register 0 occurs. (This depends on the mode.) When '1' is written to the CLR bit of the TCCS register during operation. When '0000' is written to the TCDC register during stop. Reset
An interrupt can be generated when an overflow occurs or when the counter is cleared by a match with the compare register 0. (Compare match interrupts can be used only in an appropriate mode.) s Clearing the Counter by an Overflow
Counter value FFFF H BFFF H 7FFF H 3FFF H 0000 H Reset Interrupt Time Overflow
125
CHAPTER 11 16-BIT I/O TIMER s Clearing the Counter upon a Match with Output Compare Register 0
Counter value FFFF H BFFF H 7FFF H 3FFF H 0000 H Reset Compare register value Interrupt
s 16-bit Free-running Timer Timing
Match
Match
Time
BFFFH
r 16-bit free-running timer count timing The 16-bit free-run timer is incremented based on the input clock (internal or external clock). When external clock is selected, the 16-bit free-run timer is incremented at the rising edge.
External clock input Count clock Counter value
N N+1
r 16-bit free-running timer clear timing (match with the compare register 0) The counter can be cleared upon a reset, software clear, or a match with the compare register 0. By a reset or software clear, the counter is immediately cleared. By a match with compare register 0, the counter is cleared in synchronization with the count timing.
Compare
N
register value Compare match
N 0000
Counter value
126
11.4 Output Compare
11.4 Output Compare
The output compare module consists of two 16-bit compare registers, two compare output pins, and control register. If the value written to the compare register of this module matches the 16-bit free-running timer value, the output level of the pin can be reversed and an interrupt can be issued.
s Output Compare * * * Two compare registers exist that can be used independently. Depending on the setting, the two compare registers can be used to control pin outputs. The initial value for the pin output can be specified. An interrupt can be issued upon a match as a result of comparison.
s Output Compare Block Diagram Figure 11.4-1 shows a block diagram of output compare. Figure 11.4-1 Output Compare Block Diagram
16-bit timer counter value (T15 to T00)
Compare control
T
Q
OTE0
OUT0
Compare register 0 16-bit timer counter value (T15 to T00) Bus CMOD
Compare control
T
Q
OTE1
OUT1
Compare register 1
ICP1 ICP0 ICE1 ICE0 Compare 1 interrupt Compare 0 interrupt
Controller Control blocks
127
CHAPTER 11 16-BIT I/O TIMER
11.4.1 Output Compare Register
These 16-bit compare registers are compared with the 16-bit free-running timer. Since the initial register values are undefined, set appropriate value before enabling the operation. These registers must be accessed by the word access instructions. When the value of the register matches that of the 16-bit free-running timer, a compare signal is generated and the output compare interrupt flag is set. If output is enabled, the output level corresponding to the compare register is reversed.
s Output Compare Register
bit 001931 H 001933 H
15 C15 R/W X
14 C14 R/W X bit 7
13 C13 R/W X C07 R/W X
12 C12
11 C11
10 C10
9 C09
8 C08 Attribute R/W Initial value X 2 1 0 C02 R/W X C01 R/W X C00 R/W X Attribute Initial value
R/W R/W R/W R/W X X X X 6 5 4 3 C06 R/W X C05 R/W X C04 R/W X C03 R/W X
001930 H 001932 H
128
11.4 Output Compare
11.4.2 Control Status Register of Output Compare
The control status register sets the operation mode of output compare, starts and stops output compare, controls interrupts, and sets the external output pins.
s Control Status Register of Output Compare
bit 000059H
15
14
13
12
11
10
9
8 Attribute R/W Initial value 0 2 1 0 CST1 CST0 R/W 0 R/W 0 Attribute Initial value
CMOD OTE1 OTE0
OTD1 OTD0
bit 000058H
7 ICP1 R/W 0
R/W R/W R/W R/W 0 0 0 0 6 5 4 3 ICP0 R/W 0 ICE1 R/W 0 ICE0 R/W 0
[bits 15, 14, and 13] Unused bits [bit 12] CMOD CMOD is used to switch the pin output level reverse mode upon a match while pin output is enabled (OTE1=1 or OTE0=1). * When CMOD=0 (initial value), the output level of the pin corresponding to the compare register is reversed. * * * OUT0: The level is reversed upon a match with compare register 0. OUT1: The level is reversed upon a match with compare register 1.
When CMOD=1, the output level is reversed for the compare register 0 in the same manner as for CMOD=0. The output level of the pin corresponding to compare register 1 (OUT1), however, is reversed upon a match with compare register 0 or 1. If compare registers 0 and 1 have the same value, the same operation as with a single compare register is performed. * * OUT0: The level is reversed upon a match with compare register 0. OUT1: The level is reversed upon a match with compare register 0 or 1.
[bits 11 and 10] OTE1 and OTE0 These bits are used to enable the output compare output pins. The initial value for these bits is '0.' 0 1 Note: OTE1: Corresponds to output compare 1 (OUT1). OTE0: Corresponds to output compare 0 (OUT0). When they are specified as outputs, the corresponding bits of the Port Direction registers should also be set to "1". 129 General-purpose port (initial value) Output compare pin output
CHAPTER 11 16-BIT I/O TIMER [bits 9 and 8] OTD1 and OTD0 These bits are used to change the pin output level when the output compare pin output is enabled. The initial value of the compare pin output is '0.' Ensure that the compare operation is stopped before a value is written. When read, these bits indicate the output compare pin output value. 0 1 Note: OTD1: Corresponds to output compare 1. OTD0: Corresponds to output compare 0. [bits 7 and 6] ICP1 and ICP0 These bits are used as output compare interrupt flags. '1' is set to these bits when the compare register value matches the 16-bit free-run timer value. While the interrupt request bits (ICE1 and ICE0) are enabled, an output compare interrupt occurs when the ICP1 and ICP0 bits are set. These bits are cleared by writing '0.' Writing '1' has no effect. '1' is always read by a read-modify-write instruction. 0 1 Note: ICP1: Corresponds to output compare 1. ICP0: Corresponds to output compare 0. [bits 5 and 4] ICE1 and ICE0 These bits are used as output compare interrupt enable flags. While the '1' is written to these bits, an output compare interrupt occurs when an interrupt flag (ICP1 or ICP0) is set. 0 1 Note: ICE1: Corresponds to output compare 1. ICE0: Corresponds to output compare 0. [bits 3 and 2] Unused bits [bits 1 and 0] CST1 and CST0 These bits are used to enable the comparison with 16-bit free-run timer. 0 1 Compare operation disabled (initial value) Compare operation enabled Output compare interrupt disabled (initial value) Output compare interrupt enabled No compare match (initial value) Compare match Sets '0' for the compare pin output. (initial value) Sets '1' for the compare pin output.
Ensure that a value is written to the compare register before the compare operation is enabled. 130
11.4 Output Compare Note: CST1: Corresponds to output compare 1. CST0: Corresponds to output compare 0. Since output compare is synchronized with the 16-bit free-running timer clock, stopping the 16-bit free-running timer stops compare operation.
131
CHAPTER 11 16-BIT I/O TIMER
11.4.3 16-bit Output Compare Operation
In the 16-bit output compare operation, an interrupt request flag can be set and the output level can be reversed when the specified compare register value matches the 16-bit free-run timer value.
s Sample of Output Waveform when Compare Registers 0 and 1 are Used (The Initial Output Value is 0.) Figure 11.4-2 Sample of Output Waveform when Compare Registers 0 and 1 are Used
Counter value FFFFH BFFF H 7FFFH 3FFFH 0000H Reset Compare register 0 value Compare register 1 value OUT0 OUT1 Compare 0 interrupt Compare 1 interrupt BFFFH 7FFFH
Time
The output level can be changed using two compare registers (when CMOD=1).
132
11.4 Output Compare s Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is '0.') Figure 11.4-3 Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is '0')
Counter value FFFFH BFFF H 7FFFH 3FFFH 0000H Reset Compare register 0 value Compare register 1 value OUT0 OUT1 Compare 0 interrupt Compare 1 interrupt BFFFH 7FFF H Time
Corresponds to compare 0 and 1
s Output Compare Timing In output compare operation, a compare match signal is generated when the free-running timer value matches the specified compare register value. The output value can be reversed and an interrupt can be issued. The output reverse timing upon a compare match is synchronized with the counter count timing. r Compare operation upon update of compare register When the compare register is updated, comparison with the counter value is not performed.
Counter value Compare register 0 value Compare register 0 write Compare register 1 value Compare register 1 write M
N
N+1 N+1
N+2
N+3
No match signal is generated.
M Compare 0 stop
N+3 Compare 1 stop
133
CHAPTER 11 16-BIT I/O TIMER r Interrupt timing
Counter value Compare register value Compare match Interrupt
N N
N+1
r Output pin change timing
Counter value Compare register value Compare match signal Pin output
N
N+1 N
N
N+1
134
11.5 Input Capture
11.5 Input Capture
Input capture detects a rising or falling edge or both edges of an external input signal and stores a 16-bit free-running timer value at that time in a register. In addition, input capture can generate an interrupt upon detection of an edge. Input capture consists of an input capture data register and a control register.
s Input Capture Each input capture has a corresponding external input pin. r The valid edge of an external input can be selected from the following three types:
Rising edge
Falling edge
Both edges
r An interrupt can be generated upon detection of a valid edge of an external input. s Input Capture Block Diagram Figure 11.5-1 shows a block diagram of input capture. Figure 11.5-1 Input Capture Block Diagram
Capture data register 0 Edge detection IN0
16-bit timer counter value (T15 to T00)
EG11 EG10 EG01 EG00
Bus Capture data register 1 Edge detection IN1
ICP1
ICP0
ICE1 ICE0 Interrupt Interrupt
135
CHAPTER 11 16-BIT I/O TIMER
11.5.1 Input Capture Register Details
Input capture has the two registers listed. These registers store a value from the 16-bit free running timer when a valid edge of the corresponding external pin input waveform is detected. (The registers must be accessed in word mode. No values can be written to the registers.) * Input capture data register * Input capture control register
s Input Capture Data Register
bit 001921 H 001923 H
15 CP15 R X
14
13
12
11 CP12 R X 5 4
10 CP11 R X 3
9 CP09 R X 2
8 CP08 R X Attribute Initial value 1 CP01 R X 0 CP00 R X Attribute Initial value
CP14 CP13 CP12 R X bit 7 CP07 R X R X 6 R X
001920 H 001922 H
CP06 CP05 CP04 R X R X R X
CP03 R X
CP02 R X
s Control Status Register
bit 000054 H
7 ICP1 R/W 0
6 ICP0 R/W 0
5 ICE1 R/W 0
4 ICE0 R/W 0
3 EG11 R/W 0
2 EG10 R/W 0
1 EG01 R/W 0
0 EG00 R/W 0 Attribute Initial value
[bits 7 and 6] ICP1 and ICP0 These bits are used as input capture interrupt flags. '1' is set to this bit upon detection of a valid edge of an external input pin. While the interrupt enable bits (ICE0 and ICE1) are set, an interrupt can be generated upon detection of a valid edge. These bits are cleared by writing '0.' Writing '1' has no effect. '1' is always read by a readmodify-write instruction. 0 1 Note: ICP0: Corresponds to input capture 0. ICP1: Corresponds to input capture 1. No valid edge detection (initial value) Valid edge detection
136
11.5 Input Capture [bits 5 and 4] ICE1 and ICE0 These bits are used to enable input capture interrupts. While these bits are "1", an input capture interrupt is generated when the interrupt flag (ICP0 or ICP1) is set. 0 1 Note: ICE0: Corresponds to input capture 0. ICE1: Corresponds to input capture 1. [bits 3, 2, 1, and 0] EG11, EG10, EG01, and EG00 These bits are used to specify the valid edge polarity of the external inputs. These bits are also used to enable input capture operation. EG11 EG01 0 0 EG10 EG00 0 1 Edge detection polarity No edge detection (stop) (initial value) Rising edge detection Interrupt disabled (initial value) Interrupt enabled
1
0
Falling edge detection
1
1
Both edge detection
Note: EG01 and EG00: Correspond to input capture 0. EG11 and EG10: Correspond to input capture 1.
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CHAPTER 11 16-BIT I/O TIMER
11.5.2 16-bit Input Capture Operation
In 16-bit input capture operation, an interrupt can be generated upon detection of at the specified edge, fetching the 16-bit free-run timer value and writing it to the capture register.
s Sample of Input Capture Fetch Timing * * * Capture 0: Rising edge Capture 1: Falling edge Capture example: Both edges Figure 11.5-2 Sample of Input Capture Fetch Timing
Counter value FFFF H BFFF H 7FFF H 3FFF H 0000 H Reset IN0 IN1 IN example Capture 0 Capture 1 Capture example Capture 0 interrupt Capture 1 interrupt Capture interrupt Undefined Undefined Undefined
BFFFH 7FFF H 3FFF H 7FFF H
Time
138
11.5 Input Capture s Input Capture Input Timing
r Capture timing for input signals
Counter value Input capture input
N
N+1
Valid edge
Capture signal Capture register Interrupt N+1
139
CHAPTER 11 16-BIT I/O TIMER
140
CHAPTER 12
16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
This chapter explains the functions and operations of the 16-bit reload timer (with the event count function). 12.1 Outline of 16-Bit Reload Timer (with Event Count Function) 12.2 16-Bit Reload Timer (with Event Count Function) 12.3 Internal Clock and External Clock Operations of 16-Bit Reload Timer 12.4 Underflow Operation of 16-Bit Reload Timer 12.5 Output Pin Functions of 16-Bit Reload Timer 12.6 Counter Operation State
141
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
12.1 Outline of 16-Bit Reload Timer (with Event Count Function)
The 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, one input pin (TIN) and one output pin (TOUT), and a control register. The input clock can be selected from one external clock and three types of internal clock.
s Outline of 16-bit Reload Timer (with Event Count Function) The output pin (TOUT) outputs a toggle output waveform in reload mode and outputs a square waveform indicating counting in one-shot mode. The input pin (TIN) is used for event input in event count mode, and can be used for trigger input or gate input in internal clock mode. The MB90590 Series has two 16-bit reload timers. However the TIN input and TOUT output external pins are shared between the two timers. s Intelligent I/O Service (EI2OS) Function and Interrupts The timer includes a circuit that supports EI2OS. The timer can activate EI2OS when an underflow occurs. EI2OS can be used with both timers on this product. However, as both timers (ch0 and ch1) are connected to the same interrupt control register (ICRx) in the interrupt controller, ch0 and ch1 cannot be assigned to different EI2OS services. Also, as the two timers have different interrupt vectors, they can be assigned to two different interrupt services. However, as ch0 and ch1 share an interrupt control register as described above, the same interrupt level applies to both channels.
142
12.1 Outline of 16-Bit Reload Timer (with Event Count Function) s Block Diagram of 16-bit Reload Timer Figure 12.1-1 shows a block diagram of the 16-bit reload timer. Figure 12.1-1 Block Diagram of 16-bit Reload Timer
16 16-bit reload register
8
Reload RELD 16-bit down-counter UF OUTE OUTL 2 GATE CSL1 Clock selector CSL0 TRG CNTE Clear I2OSCLR
OUT CTL.
F2 M C - 16 B U S
16
INTE UF IRQ
2 IN CTL EXCK 21 23 25 Prescaler clear 3
Re-trigger
Port (TIN) Output enable Port (TOUT) MOD2 MOD1 UART baud rate (ch0) A/DC (ch1)
Peripheral clock
MOD0
3
143
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
12.2 16-Bit Reload Timer (with Event Count Function)
The 16-bit reload timer has the following two types of registers: * Timer control register (TMCSR) * 16-bit timer register (TMR)/16-bit reload register (TMRLR)
s 16-bit Reload Timer Register
Timer control status register (upper) Address: ch0 000051H ch1 000053H Read/write Initial value -- -- --
15 -- -- --
14 -- -- --
13 -- -- --
12 CSL1 (R/W) (0)
11 CSL0 (R/W) (0)
10 MOD2 (R/W) (0)
9 MOD1 (R/W) (0)
8
Bit number
Timer control status register (lower) Address: ch0 000050H ch1 000052H MOD0
7 OUTE
6 OUTL
5 RELD
4 INTE
3 UF
2 CNTE
1 TRG
0
Bit number TMCSR
Read/write Initial value
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
16-bit timer register (upper)/ 16-bit reload register (upper) Address: ch0 001941H ch1 001943H Read/write Initial value
15 (R/W) (X) (R/W) (X)
14
13
12
11
10
9
8
Bit number
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
16-bit timer register (lower)/ 16-bit reload register (lower) Address: ch0 001940H ch1 001942H ch1 00003EH
7 (R/W) (X) (R/W) (X)
6
5
4
3
2
1
0
Bit number TMR/ TMRLR
Read/write Initial value
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
144
12.2 16-Bit Reload Timer (with Event Count Function)
12.2.1 Timer Control Status Register (TMCSR)
Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other than UF, CNTE, and TRG when CNTE = "0".
s Register Layout of Timer Control Register (TMCSR)
Timer control status register (upper) Address: ch0 000051H ch1 00003DH ch1 000053H Read/write Initial value -- -- --
15 -- -- --
14 -- -- --
13 -- -- --
12 CSL1 (R/W) (0)
11 CSL0 (R/W) (0)
10 MOD2 (R/W) (0)
9 MOD1 (R/W) (0)
8
Bit number
Timer control status register (lower) Address: ch0 000050H ch1 00003CH ch1 000052H MOD0
7 OUTE
6 OUTL
5 RELD
4 INTE
3 UF
2 CNTE
1 TRG
0
Bit number TMCSR
Read/write Initial value
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
(R/W) (0)
s Register Contents of Timer Control Register (TMCSR) [Bits 11, 10] CSL1, CSL0 (Clock select 1, 0) The count clock select bits. Table 12.2-1 lists the selected clock sources. Table 12.2-1 Clock Sources for CSL Bit Settings CSL1 0 0 1 1 CSL0 0 1 0 1 Clock Source (Machine cycle = 16 MHz) /21 (0.125 s) /23 (0.5 s) /25 (2.0 s) External event count mode
[Bits 9, 8, 7] MOD2, MOD1, MOD0 These bits set the operation mode and I/O pin functions. The MOD2 bit selects the I/O functions. When MOD2 = "0", the input pin functions as a trigger input. In this case, the reload register contents is loaded to the counter when an active edge is input to the input pin and count operation proceeds. When MOD2 = "1", the timer operates in gate counter mode and the input pin functions as a gate input. In this mode, the counter only counts while an active level is input to the input pin. The MOD1 and 0 bits set the pin functions for each mode. Tables 12.2-2 and 12.2-3 list the
145
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MOD2, 1, 0 bit settings. Table 12.2-2 MOD2, 1, 0 Bit Settings (1) MOD2 0 0 0 MOD1 0 0 1 MOD0 0 1 0 Input Pin Function Trigger disabled Trigger input Active Edge or Level Rising edge Falling edge
0
1
1
Both edges
1 1
x x
0 1
Gate input
"L" level "H" level
Internal clock mode (CSL0, 1 = "00", "01", or "10") Table 12.2-3 MOD2, 1, 0 Bit Settings (2) MOD2 MOD1 0 0 1 MOD0 0 1 0 Input Pin Function Trigger input Active Edge or Level Rising edge Falling edge
x
1 1 Both edges
* *
Event counter mode (CSL0,1 = "11") Bits marked as x in the table can be set to any value.
[Bit 6] OUTE Output enable bit. The TOUT pin functions as a general-purpose port when this bit is "0" and as the timer output pin when this bit is "1". In reload mode, the output waveform toggles. In one-shot mode, TOUT outputs a square waveform that indicates that counting is in progress. [Bit 5] OUTL This bit sets the output level for the TOUT pin. Table 12.2-4 OUTE, RELD, and OUTL Settings OUTE 0 RELD OUTL Output Waveform General-purpose port
x
x
146
12.2 16-Bit Reload Timer (with Event Count Function) Table 12.2-4 OUTE, RELD, and OUTL Settings (Continued) OUTE 1 1 1 1 RELD 0 0 1 1 OUTL 0 1 0 1 Output Waveform Output an "H" level square waveform during counting. Output an "L" level square waveform during counting. Toggle output. Starts with "L" level output. Toggle output. Starts with "H" level output.
[Bit 4] RELD (Reload) This bit enables reload operations. When RELD is "1", the timer operates in reload mode. In this mode, the timer loads the reload register contents into the counter and continues counting whenever an underflow occurs (when the counter value changes from 0000H to FFFFH). When RELD is "0", the timer operates in one-shot mode. In this mode, the count operation stops when an underflow occurs due to the counter value changing from 0000H to FFFFH. [Bit 3] INTE (Interrupt enable) Timer interrupt request enable bit. When INTE is "1", an interrupt request is generated when the UF bit changes to "1". When INTE is "0", no interrupt request is generated, even when the UF bit changes to "1". [Bit 2] UF (Underflow) Timer interrupt request flag. UF is set to "1" when an underflow occurs (when the counter value changes from 0000H to FFFFH). Cleared by writing "0" or by the intelligent I/O service. Writing "1" to this bit has no meaning. Read as "1" by read-modify-write instructions. [Bit 1] CNTE (Count enable) Timer count enable bit. Writing "1" to CNTE sets the timer to wait for a trigger. Writing "0" stops count operation. [Bit 0] TRG (Trigger) Software trigger bit. Writing "1" to TRG applies a software trigger, causing the timer to load the reload register contents to the counter and start counting. Writing "0" has no meaning. Reading always returns "0". Applying a trigger using this register is only valid when CNTE = "1". Writing "1" has no effect if CNTE = "0".
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CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
12.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)
TMR contents (for reading) Reading this register reads the count value of the 16-bit timer. The initial value is undefined. Always read this register using the word access instructions. TMRLR contents (for writing) The 16-bit reload register holds the initial count value. The initial value is undefined. Always write to this register using the word access instructions.
s Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)
16-bit timer register (upper)/ 16-bit reload register (upper) Address: ch0 001941H ch1 00003FH ch1 001943H Read/write Initial value (R/W) (X)
15
14
13
12
11
10
9
8
Bit number
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
16-bit timer register (lower)/ 16-bit reload register (lower) Address: ch0 001940H ch1 00003EH ch1 001942H
7 (R/W) (X) (R/W) (X)
6
5
4
3
2
1
0
Bit number TMR/ TMRLR
Read/write Initial value
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
148
12.3 Internal Clock and External Clock Operations of 16-bit Reload Timer
12.3 Internal Clock and External Clock Operations of 16-bit Reload Timer
The machine clock divided by 21, 23, or 25 can be selected as the clock sources for operating the timer from an internal divide clock. The external input pin can be selected as either a trigger input or gate input by a register setting. If an external clock is selected, the TIN pin functions as an external event input pin to count the number of valid edges set in the register.
s Internal Clock Operation of 16-bit Reload Timer Writing "1" to both the CNTE and TRG bits in the control register enables and starts counting at one time. Using the TRG bit as a trigger input is always available when the timer is enabled (CNTE = "1"), regardless of the operation mode. Figure 12.3-1 shows counter activation and counter operation. A time period T (T: machine cycle) is required from the counter start trigger being input until the reload register data is loaded into counter. Figure 12.3-1 Activation and Operation of 16-bit Reload Timer Counter
Count clock Counter Reload data -1 -1 -1
Data load CNTE (bit)
TRG (bit)
T
149
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) s Input Pin Functions of 16-bit Reload Timer (in Internal Clock Mode) The TIN pin can be used as either a trigger input or a gate input when an internal clock is selected as the clock source. When used as a trigger input, input of an active edge causes the timer to load the reload register contents to the counter and then start count operation after clearing the internal prescaler. Input a pulse width of at least 2T (T is the machine cycle) to TIN. Figure 12.3-2 shows the operation of trigger input. Figure 12.3-2 Trigger Input Operation of 16-bit Reload Timer
Count clock
TIN Prescaler clear Counter 0000H
Rising edge detected
Reload data
-1
-1
-1
Load
2T2.5T
When used as a gate input, the counter only counts while the active level specified by the MOD0 bit of the control register is input to the TIN pin. In this case, the count clock continues to operate unless stopped. The software trigger can be used in gate mode, regardless of the gate level. Input a pulse width of at least 2T (T is the machine cycle) to the TIN pin. Figure 12.3-3 shows the operation of gate input. Figure 12.3-3 Gate Input Operation of 16-bit Reload Timer
Count clock
TIN Counter
When MOD0 = "1" (Count when "H" is input) -1 -1 -1
150
12.3 Internal Clock and External Clock Operations of 16-bit Reload Timer s External Event Counter The TIN pin functions as an external event input pin when an external clock is selected. The counter counts on the active edge specified in the register. Input a pulse width of at least 4T (T is the machine cycle) to the TIN pin.
151
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
12.4 Underflow Operation of 16-bit Reload Timer
An underflow is defined for this timer as the time when the counter value changes from 0000H to FFFFH. Therefore, an underflow occurs after (reload register setting + 1) counts.
s Underflow Operation of 16-bit Reload Timer If the RELD bit in the control register is "1" when the underflow occurs, the contents of the reload register is loaded into the counter and counting continues. When RELD is "0", counting stops with the counter at FFFFH. The UF bit in the control register is set when the underflow occurs. If the INTE bit is "1" at this time, an interrupt request is generated. Figure 12.4-1 shows the operation when an underflow occurs. Figure 12.4-1 Underflow Operation of 16-bit Reload Timer
Count clock Counter Data load 0000H Reload data -1 -1 -1
Underflow set [RELD=1]
Count clock Counter 0000H FFFFH
Underflow set [RELD=0]
152
12.5 Output Pin Functions of 16-bit Reload Timer
12.5 Output Pin Functions of 16-bit Reload Timer
In reload mode, the TOUT pin performs toggle output (inverts at each underflow). In one-shot mode, the TOUT pin functions as a pulse output that outputs a particular level while the count is in progress.
s Output Pin Functions of 16-bit Reload Timer The OUTL bit of the control register sets the output polarity. When OUTL = "0", the initial value for toggle output is "0" and the one-shot pulse output is "1" while the count is in progress. The output waveforms are opposite when OUTL = "1". Figures 12.5-1 and 12.5-2 show the output pin functions. Figure 12.5-1 Output Pin Function of 16-bit Reload Timer (1)
Count start Under?ow Level is opposite when OUTL = "1".
TOUT General-purpose port CNTE
Trigger [RELD=1, OUTL=0]
Figure 12.5-2 Output Pin Function of 16-bit Reload Timer (2)
Under?ow TOUT
Level is opposite when OUTL = "1".
General-purpose port CNTE
Trigger
Waiting for a trigger [RELD=0, OUTL=0]
153
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
12.6 Counter Operation State
The counter state is determined by the CNTE bit in the control register and the internal WAIT signal. Available states are: CNTE = "0" and WAIT = "1" (STOP state), CNTE = "1" and WAIT = "1" (WAIT state for trigger), and CNTE = "1" and WAIT = "0" (RUN state).
s Counter Operation State Figure 12.6-1 shows the transitions between each state. Figure 12.6-1 Counter State Transitions
Reset State transitions by hardware
STOP
CNTE=0, WAIT=1 State transitions by register access
Counter: Retains the value while counting stopped. Value undefined after reset.
CNTE='0' CNTE='1' TRG='0' CNTE='1' TRG='1'
CNTE='0'
WAIT
CNTE=1, WAIT=1
RUN
CNTE=1, WAIT=0
Counter: Retains the value while counting stopped. Value undefined after reset until load.
RELD*UF
Counter: Running
TRG='1'
TRG='1' RELD*UF
LOAD
CNTE=1, WAIT= 0 Load complete
Load contents of the reload register to the counter.
154
CHAPTER 13
WATCH-DOG TIMER
This chapter explains the functions and operations of the watch-dog timer. 13.1 Outline of Watch Timer 13.2 Watch-dog Timer Registers
155
CHAPTER 13 WATCH-DOG TIMER
13.1 Outline of Watch Timer
The Watch Timer consists of the Timer Control register, Sub-second register, Second/ Minute/Hour registers, 1/2 clock divider, 21bit prescaler and Second/Minute/Hour counters. The oscillation frequency of the MCU is assumed to be at 4MHz for the aimed operation of the Watch Timer. The Watch Timer operates as the real-world timer and provides the real-world time information.
s Block Diagram of Watch-dog Timer Figure 13.1-1 shows a block diagram of the watch-dog timer. Figure 13.1-1 Block Diagram of Watch-dog Timer
Oscillation 1/2 Clock clock Divider
21bit Prescaler CO EN
OE
OE WOT
Sub-second register
UPDT
ST
Second Counter Minute Counter CI EN CO LOAD CO 6bits
Hour Counter CO
6bits 5bits Second/Minute/Hour register
INT1 INTE2 INT2 INT3 INT3
INTE0
INT0
INTE1
IRQ
156
13.2 Watch-dog Timer Registers
13.2 Watch-dog Timer Registers
The watch-dog timer has the following five types of registers: * Timer control register (WTCR) * Subsecond register (WTBR) * Second register (WTSR) * Minute register (WTMR) * Hour register (WTHR)
s Watch-dog Timer Registers
Timer control register Address: 000060H
7 TST2
6 TST1 (R/W) (0) 13 INTE2 (R/W) (0)
5 TST0 (R/W) (0) 12 INT2 (R/W) (0)
4
3
2 UPDT (R/W) (0)
1 OE (R/W) (0) 9 8 INT0 (R/W) (0)
0 ST (R/W) (0)
Bit number WTCR
Read/write Initial value Timer control register Address: 000061H 15
(R/W) (0) 14
11 INTE1 (R/W) (0)
10 INT1 (R/W) (0)
Bit number WTCR
INTE3 Read/write Initial value Sub-second register Address: 00194AH D7 Read/write Initial value Sub-second register Address: 00194BH 15 D15 (R/W) (X) (R/W) (0)
INT3 (R/W) (0)
INTE0 (R/W) (0)
7 D6
6 D5
5 D4
4
3 D3 (R/W) (X) 11
2 D2 (R/W) (X) 10 9 D9 (R/W) (X)
1 D1 (R/W) (X) 8 D8 (R/W) (X)
0 D0 (R/W) (X)
Bit number WTBR
(R/W) (X) 14
(R/W) (X)
(R/W) (X) 13
(R/W) (X) 12
Bit number WTBR
D14 (R/W) (X)
D13 (R/W) (X)
D12 (R/W) (X)
D11 (R/W) (X)
D10 (R/W) (X)
Read/write Initial value Sub-second register Address: 00194CH
7
6
5
4 D20
3 D19 (R/W) (X)
2 D18 (R/W) (X) 10 9 S1 (R/W) (X)
1 D17 (R/W) (X) 8 S0 (R/W) (X)
0 D16 (R/W) (X)
Bit number WTBR
Read/write Initial value Second register Address: 00194DH S5 Read/write Initial value Minute register Address: 00194EH 7 6 M5 Read/write Initial value Hour register Address: 00194FH H4 Read/write Initial value 15 14 13 (R/W) (X) 5 (R/W) (X) S4 15 14 13 12
(R/W) (X) 11 S3
Bit number WTSR
S2 (R/W) (X)
(R/W) (X)
(R/W) (X)
4 M4 (R/W) (X) 12 11 H3 (R/W) (X) M3
3 M2
2
1 M1 (R/W) (X) 9 H1 8 H0 (R/W) (X)
0 M0 (R/W) (X)
Bit number WTMR
(R/W) (X) 10 H2
(R/W) (X)
Bit number WTHR
(R/W) (X)
(R/W) (X)
(R/W) (X)
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CHAPTER 13 WATCH-DOG TIMER
13.2.1 Timer Control Register
The timer control register starts and stops the watch-dog timer, controls interrupts, and sets the external output pins.
s Timer Control Register
Timer control register Address: 000060H
7 TST2
6 TST1 (R/W) (0) 13 INTE2 (R/W) (0)
5 TST0 (R/W) (0) 12 INT2 (R/W) (0)
4
3
2 UPDT (R/W) (0)
1 OE (R/W) (0) 9 INTE0 (R/W) (0) 8
0 ST (R/W) (0)
Bit number WTCR
Read/write Initial value Timer control register Address: 000061H 15
(R/W) (0) 14
11 INTE1 (R/W) (0)
10 INT1 (R/W) (0)
Bit number WTCR
INTE3 Read/write Initial value (R/W) (0)
INT3 (R/W) (0)
INT0 (R/W) (0)
[bits 15 to 8] INT3 to 0, INTE3 to 0 : Interrupt flags and Interrupt enable flags INT0 to INT3 are the interrupt flags. They are set when the second counter, minute counter and hour counter overflow respectively. If a INT bit is set while the corresponding INTE bit is "1", the Watch Timer signals an interrupt. These flags are intended to signal an interrupt every second/minute/hour/day. Writing "0" to the INT bits clears the flags and writing "1" does not have any effect. Any readmodify-write instruction performed on the INT bit results reading "1". [bits 7 to 5] TST2 to 0 : Test bits These bits are prepared for the device test. In any user applications, they should be set to "000". [bit 2] UPDT : Update bit The UPDT bit is prepared for modifying the Second/Minute/Hour counter values. To modify the counter values, write the modified data in the Second/Minute/Hour registers. Then set the UPDT bit to "1". The register values are loaded to the counter at the next CO signal from the 21-bit prescaler. The UPDT bit is reset by the hardware when the counter values are updated. However, if the set operation by software and the reset operation by hardware occur at the same time, the UPDT bit will not be reset. Note: If this bit is set during "59 second", normal up count operation is executed and this bit is reset to "0" without reflecting the Second/Minute/Hour register values. Writing "0" to the UPDT bit has no effect and a read-modify-write instruction results in reading "0". [bit 1] OE : Output enable bit When the OE bit is set to "1", the WOT external pin serves as the output for the Watch 158
13.2 Watch-dog Timer Registers Timer. Otherwise it can be used as a general purpose I/O or for another peripheral block. [bit 0] ST : Start bit When the ST bit is set to "1", the Watch Timer loads Second/Minute/Hour values from the registers and starts its operation. When it is reset to "0", all the counters and the prescalers are reset to "0" and halts.
159
CHAPTER 13 WATCH-DOG TIMER
13.2.2 Sub-second Registers
The subsecond register stores a reload value for the 21-bit prescaler that divides the oscillation clock. The reload value is usually set so that the 21-bit prescaler will output exactly within a one-second cycle.
s Sub-second Register
Sub-second register Address: 00194AH 7 D7 Read/write Initial value Sub-second register Address: 00194BH 15 D15 (R/W) (X) (R/W) (X) 14 D14 (R/W) (X) 6 D6 (R/W) (X) 5 D5 (R/W) (X) 13 D13 (R/W) (X) 4 D4 (R/W) (X) 12 D12 (R/W) (X) 3 D3 (R/W) (X) 11 D11 (R/W) (X) 2 D2 (R/W) (X) 10 D10 (R/W) (X) 9 D9 (R/W) (X) 1 D1 (R/W) (X) 8 D8 (R/W) (X) 0 D0 (R/W) (X) Bit number WTBR Bit number WTBR
Read/write Initial value Sub-second register Address: 00194CH
7
6
5
4 D20
3 D19 (R/W) (X)
2 D18 (R/W) (X)
1 D17 (R/W) (X)
0 D16 (R/W) (X)
Bit number WTBR
Read/write Initial value
(R/W) (X)
[bit 20 to 0] D20 to D0 The Sub-second register stores the reload value for the 21bit prescaler. This value is reloaded after the reload counter reaches "0". Note that when modifying the all three bytes, make sure the reload operation will not be performed in between the write instructions. Otherwise the 21-bit prescaler loads the incorrect value of the combination of new data and old data bytes. It is generally recommended that the Sub-Second register are updated while the ST bit is "0". If the sub-second registers are set to "0", the 21-bit prescaler does not operate at all. The input clock frequency always equals the oscillation clock frequency and it is intended to be 4MHz. The reload value of the 21bit prescaler is typically set to Hex1E847F which equals to "27 * 56-1". Therefore the combination of these two prescalers is intended to provide a clock signal of exact one second.
160
13.2 Watch-dog Timer Registers
13.2.3 Second/Minute/Hour Registers
The Second/Minute/Hour registers stores the time information. It is a binary representation of the second, minute and hour. Reading these registers simply returns the counter values. These registers are write associable however, the written data is loaded in the counters after the UPDT bit is set to "1".
s Second/Minute/Hour Registers
Second register Address: 00194DH
15
14
13 S5
12 S4 (R/W) (X)
11 S3 (R/W) (X)
10 S2 (R/W) (X)
9 S1 (R/W) (X)
8 S0 (R/W) (X)
Bit number WTSR
Read/write Initial value Minute register Address: 00194EH 7 6
(R/W) (X)
5 M5
4 M4 (R/W) (X) 12 H4 11 H3
3 M3 (R/W) (X) 10 H2
2 M2 (R/W) (X) 9
1 M1 (R/W) (X) 8 H0
0 M0 (R/W) (X)
Bit number WTMR
Read/write Initial value Hour register Address: 00194FH 15 14 13
(R/W) (X)
Bit number WTHR
H1 (R/W) (X)
Read/write Initial value
(R/W) (X)
(R/W) (X)
(R/W) (X)
(R/W) (X)
Since there are three byte-registers, make sure the obtained values from the registers are consistent. i.e. Obtained value of "1 hour, 59 minute, 59 second" could be "0 hour 59 minute, 59 second" or "1 hour, 0 minute, 0 second" or "2 hour, 0 minute, 0 second". Also when the operation clock of the MCU is the half of the oscillation clock (When the PLL is stopped), the read values from these registers may be corrupt. This is due to the synchronization of the read operation and the count operation. Therefore it is recommended is use a second interrupt to trigger the read instructions.
161
CHAPTER 13 WATCH-DOG TIMER
162
CHAPTER 14
8/16-BIT PPG
This chapter explains the 8/16-bit PPG and explains its functions. 14.1 Outline of 8/16-Bit PPG 14.2 Block Diagram of 8/16-Bit PPG 14.3 8/16-Bit PPG Registers 14.4 Operations of 8/16-Bit PPG 14.5 Selecting a Count Clock for 8/16-Bit PPG 14.6 Controlling Pin Output of 8/16-Bit PPG Pulses 14.7 8/16-Bit PPG Interrupts 14.8 Initial Values of 8/16-Bit PPG Hardware
163
CHAPTER 14 8/16-BIT PPG
14.1 Outline of 8/16-bit PPG
The 8/16-bit Programable Pulse Generator (PPG) consists of two eight-bit down counters, four eight-bit reload registers, one 16-bit control register, two external pulse output signals, and two interrupt outputs. The following functions are implemented:
s Function of 8/16-bit PPG
r 8-bit PPG output, 2-channel independent operation mode: Two independent channels of PPG output operation are implemented. r 16-bit PPG output operation mode: One channel of 16-bit PPG output operation is implemented. r 8+8-bit PPG output operation mode: 8-bit PPG output operation is implemented at specifies intervals, using channel 0 output as channel 1 clock input. r PPG output operation: Pulse waves are output at specified intervals and duty ratio. With an external circuit, this module can be used as a D/A converter. The MB90590 Series contains six PPG's. The follwoing sections only describe the functionality of the PPG 0/1. The remaining PPG's have the identical function and the register addresses should be found in the I/O map.
164
14.2 Block Diagram of 8/16-Bit PPG
14.2 Block Diagram of 8/16-Bit PPG
Figure 14.2-1 shows a block diagram of the 8/16-bit PPG (ch0). Figure 14.2-2 shows a block diagram of the 8/16-bit PPG (ch1).
s Block Diagram of 8/16-bit PPG
Figure 14.2-1 8-bit PPG ch0 Block Diagram
PPG00 output enable PPG00
Peripheral clock 16-division Peripheral clock 8-division Peripheral clock 4-division Peripheral clock 2-division Peripheral clock
In MB90590 Series, this signal is not connected to any external pin. PPG0 Output latch Invert Clear PEN0 In MB90590 Series, this IRQ signal merged with the Channel 1 IRQ signal by OR logic. IRQ ch1-borrow
Count clock selection Time base counter output 512-division of main clock L/H selection
PCNT (down counter) Reload
S RQ
L/H selector
PRLL0
PRLBH0 PIE0
PRLH0 PUF0 L data bus H data bus PPGC0 (Operation mode control)
165
CHAPTER 14 8/16-BIT PPG Figure 14.2-2 8-bit PPG ch1 Block Diagram
PPG10 output enable PPG10
Peripheral clock 16-division Peripheral clock 8-division Peripheral clock 4-division Peripheral clock 2-division Peripheral clock
In MB90590 Series this pin is connected to the "PPG0" external pin. PPG1 Output latch
Invert Count clock selection
Clear PEN1 In MB90590 Series, this IRQ signal merged with the Channel 0 IRQ signal by OR logic.
ch0 borrow Time base counter output 512-division of main clock L/H selection
PCNT (down counter) Reload
S RQ
IRQ
L/H selector
PRLL1
PRLBH1 PIE
PRLH1 PUF L data bus H data bus
PPGC1 (Operation mode control)
166
14.3 8/16-Bit PPG Registers
14.3 8/16-Bit PPG Registers
The 8/16-bit PPG has the following five types of registers: * PPG0 operation mode control register * PPG1 operation mode control register * PPG0, 1 operation mode control register * Reload register H * Reload register L
s 8/16-bit PPG Registers
PPG0 operation mode control register 7 Address: ch0 000038H PEN0 Read/write Initial value (R/W) (0) (-) (-) PE00 PIE0 PUF0 (-) (-) (-) (-) (R/W) (R/W) (R/W) (0) (0) (0) 6 5 4 3 2 1 0 Reserved PPGC0 (W) (1) Bit No.
PPG1 operation mode control register 15 Address: ch0 000039H PEN1 Read/write Initial value (R/W) (0)
14
13
12
11
10
9
8
Bit No. PPGC1
PE10 PIE1 (-) (-)
PUF1 MD1
M D 0 Reserved (W) (1)
(R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0)
PPG0,1 output control register Address: ch0 1 003AH , Read/write Initial value
7
6
5
4
3
2
1
0
Bit No. PPG01
PCS2 P C S 1 P C S 0 P C M 2 P C M 1 P C M 0 (R/W) (0) (R/W) (0) (R/W) (R/W) (0) (0) (R/W) (R/W) (0) (0) (-) (-) (-) (-)
15 Reload register H Address: ch0 001901H ch1 001903H Read/write Initial value
14
13
12
11
10
9
8
Bit No. PRLH
(R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X)
(R/W) (R/W) (X) (X)
(R/W) (X)
7 Reload register L Address: ch0 001900H ch1 001902H Read/write Initial value (R/W) (R/W) (X) (X)
6
5
4
3
2
1
0
Bit No. PRLL
(R/W) (R/W) (R/W) (X) (X) (X)
(R/W) (R/W) (X) (X)
(R/W) (X)
167
CHAPTER 14 8/16-BIT PPG
14.3.1 PPG0 Operation Mode Control Register (PPGC0)
PPGC0 is a five-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers.
s PPG0 Operation Mode Control Register (PPGC0)
PPG0 operation mode control register 7 Address: ch0, 000038H PEN0 Read/write Initial value (R/W) (0) -
6
5 PE00
4 PIE0 (R/W) (0)
3 PUF0 (R/W) (0)
2 (-) (-)
1 (-) (-)
0 Reserved (W) (1)
Bit No. PPGC0
(-) (-)
(R/W) (0)
[bit 7] PEN0 (PPG enable): Operation enable bit This bit enables the counter operation of the PPG. PEN0 0 1 Stop ('L' level output maintained) PPG operation enabled Operation
Setting this bit to 1 enables the counter operation. This bit is initialized to '0' upon a reset. This bit is readable and writable. [bit 5] PE00 (PPG output enable 00): PPG00 pin output enable bit This bit controls the PPG00 pulse output external pin as described below. 0 1 General-purpose port pin (pulse output disabled) PPG00 = pulse output pin (pulse output enabled)
This bit is initialized to '0' upon a reset. This bit is readable and writable. For MB90590 Series, this bit should always be set to "0". [bit 4] PIE0 (PPG interrupt enable): PPG interrupt enable bit This bit controls PPG interrupt as described below. 0 1 Interrupt disabled Interrupt enabled
While this bit is "1", an interrupt request is issued as soon as PUF0 is set to "1". No interrupt request is issued while this bit is set to "0". This bit is initialized to '0' upon a reset. This bit is readable and writable.
168
14.3 8/16-Bit PPG Registers [bit 3] PUF0 (PPG underflow flag): PPG counter underflow bit This bit indicates the PPG counter underflow as described below. 0 1 PPG counter underflow is not detected. PPG counter underflow is detected.
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the ch0 counter value becoming from 00H to FFH. In 16bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel 0 and 1 counter value becoming from 0000H to FFFFH. To set this bit to '0,' write '0.' Writing '1' to this bit has not effect. Upon a read operation during a read-modify-write instruction, '1' is read. This bit is initialized to '0' upon a reset. This bit is readable and writable. [bit 0] This is a reserved bit. When setting PPGC0, always set this bit to 1.
169
CHAPTER 14 8/16-BIT PPG
14.3.2 PPG1 Operation Mode Control Register (PPGC1)
PPGC0 is a seven-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers.
s PPG1 Operation Mode Control Register (PPGC1)
PPG1 operation mode control register Address: ch1 000039H Read/write Initial value
15 PEN1 (R/W) (0) -
14
13 PE10
12 PIE1 (R/W) (0)
11 PUF1 (R/W) (0)
10 MD1 (R/W) (0)
9 MD0 (R/W) (0)
8 Reserved (W) (1)
Bit No. PPGC1
(-) (-)
(R/W) (0)
[bit 15] PEN1 (PPG enable): Operation enable bit This bit enables the counter operation of the PPG. PEN1 0 1 Stop ('L' level output maintained) PPG operation enabled Operation
Setting this bit to 1 enables the counter operation. This bit is initialized to '0' upon a reset. This bit is readable and writable. [bit 13] PE10 (PPG output enable 10): PPG10 pin output enable bit This bit controls the PPG10 pulse output external pin as described below. 0 1 General-purpose port pin (pulse output disabled) PPG10 = pulse output pin (pulse output enabled)
This bit is initialized to '0' upon a reset. This bit is readable and writable. For MB90590 Series , the pulse signal is output to the "PPG0" external pin. [bit 12] PIE1 (PPG interrupt enable): PPG interrupt enable bit This bit controls PPG interrupt as described below. 0 1 Interrupt disabled Interrupt enabled
While this bit is "1", an interrupt request is issued as soon as PUF1 is set to "1". No interrupt request is issued while this bit is set to "0". This bit is initialized to '0' upon a reset. This bit is readable and writable.
170
14.3 8/16-Bit PPG Registers [bit 11] PUF1 (PPG underflow flag): PPG counter underflow bit This bit indicates the PPG counter underflow as described below. 0 1 PPG counter underflow is not detected. PPG counter underflow is detected.
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel 1 counter value becoming from 00H to FFH. In 16-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel 0 and 1 counter value becoming from 0000H to FFFFH. To set this bit to '0,' write '0.' Writing '1' to this bit has not effect. Upon a read operation during a read-modify-write instruction, '1' is read. This bit is initialized to '0' upon a reset. This bit is readable and writable. [bit 10, 9] MD1, 0 (PPG count mode): Operation mode selection bit This bit selects the PPG timer operation mode as described below. MD1 0 0 0 0 MD0 0 1 0 1 Operation mode 8-bit PPG 2ch independent mode 8-bit prescaler + 8-bit PPG 1ch mode Reserved 16-bit PPG 1ch mode
This bit is initialized to '00' upon a reset. This bit is readable and writable. Note: Do not set '10' in this bit. To write '01' to this bit, ensure that '01' is not written to the PEN0 bit of PPGC0 or PEN1 bit of PPGC1. Write '11' or '00' in both the PEN0 and PEN1 bits simultaneously. To write '11' to this bit, update PPGC0 and PPGC1 by word transfer and write '11' or '00' to both the PEN0 and PEN1 bits simultaneously. [bit 8] This is a reserved bit. When setting PPGC1, always write 1 to this bit.
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CHAPTER 14 8/16-BIT PPG
14.3.3 PPG0, 1 Output Control Register (PPG01)
The PPG0, 1 output control register (PPG01) is an 8-bit control register that controls the pin output of the 8/16-bit PPG.
s PPG0, 1 Clock Select Register (PPG01)
PPG0, 1 output control register 7 Address: ch0, 1 003AH PCS2 Read/write Initial value (R/W) (0)
6 PCS1 (R/W) (0)
5 PCS0 (R/W) (0)
4
3 PCM2 (R/W) (0)
2 PCM1 (R/W) (0)
1 PCM0 (R/W) (0)
0
Bit No. PPG01 (-) (-) (-) (-)
[bits 7 to 5] PCS2 to 0 (PPG count select): Count clock selection bit These bits select the operation clock for the down counter of Channel 1 as described below. PCS2 0 0 0 0 1 1 PCS1 0 0 1 1 0 0 PCS0 0 1 0 1 0 1 Operation mode Peripheral clock (62.5-ns machine clock, 16 MHz) Peripheral clock/2 (125-ns machine clock, 16 MHz) Peripheral clock/4 (250-ns machine clock, 16 MHz) Peripheral clock/8 (500-ns machine clock, 16 MHz) Peripheral clock/16 (1-s machine clock, 16 MHz) Clock input fromthe time base timer (128-us, 4-MHz source oscillation)
This bit is initialized to '000' upon a reset. This bit is readable and writable. Note: In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, ch1 PPG operates in response to a counter clock from ch0. Therefore, the setting in these bits has no effect. [bits 4 to 2] PCM2 to 0 (PPG count mode): Count clock selection bit These bits select the operation clock for the down counter of Channel 0 as described below. PCS2 0 0 0 0 PCS1 0 0 1 1 PCS0 0 1 0 1 Operation mode Peripheral clock (62.5-ns machine clock, 16 MHz) Peripheral clock/2 (125-ns machine clock, 16 MHz) Peripheral clock/4 (250-ns machine clock, 16 MHz) Peripheral clock/8 (500-ns machine clock, 16 MHz)
172
14.3 8/16-Bit PPG Registers
PCS2 1 1
PCS1 0 0
PCS0 0 1
Operation mode Peripheral clock/16 (1-s machine clock, 16 MHz) Clock input from the time base timer (128-us, 4-MHz source oscillation)
This bit is initialized to '000' upon a reset. This bit is readable and writable.
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CHAPTER 14 8/16-BIT PPG
14.3.4 Reload Register (PRLL/PRLH)
The reload registers (PRLL and PRLH) are 8-bit registers that store reload values for the PCNT down counters. The PRLL and PRLH registers are readable and writable.
s Reload Register (PRLL/PRLH)
15 Reload register H Address: ch0 001901H ch1 001903H Read/write Initial value
14
13
12
11
10
9
8
Bit No. PRLH
(R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X)
(R/W) (R/W) (X) (X)
(R/W) (X)
7 Reload register L Address: ch0 001900H ch1 001902H (R/W) (R/W) (X) (X)
6
5
4
3
2
1
0
Bit No. PRLL
(R/W) (R/W) (R/W) (X) (X) (X)
(R/W) (R/W) (X) (X)
(R/W) (X)
Register name 0 1 Note: Holds the L side reload value. Holds the H side reload value.
Function
In 8-bit prescaler + 8-bit PPG mode, different values in PRLL and PRLH of Channel 0 may cause the PPG waveform of ch1 to vary in each cycle. Write the same value to PRLL and PRLH of ch0.
174
14.4 Operations of 8/16-bit PPG
14.4 Operations of 8/16-bit PPG
One 8/16-bit PPG consists of two channels of 8-bit PPG units. These two channels can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode.
s Operations of 8/16-bit PPG Each of the 8-bit PPG units has two eight-bit reload registers. One reload register is for the L pulse width (PRLL) and the other is for the H pulse width (PRLH). The values stored in these registers are reloaded into the 8-bit down counter (PCNT), from the PRLL and PRLH in turn. The pin output value is inverted upon a reload caused by counter borrow. This operation results in the pulses of the specified L pulse width and H pulse width. Table 14.4-1 lists the relationship between the reload operation and pulse outputs. Table 14.4-1 Reload Operation and Pulse Output Reload operation PRLH => PCNT PPG0/1 [0 => 1] Pin output change Rise
PRLL => PCNT
PPG0/1 [1 => 0]
Fall
When 1 is set in bit 4 (PIE0) of PPGC0 or in bit 12 (PIE1) of PPGC1, an interrupt request is output upon a borrow from 00 to FF (from 0000 to FFFF in 16-bit PPG mode) of each counter. s Operation Modes of 8/16-bit PPG This block can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode. r Independent two-channel mode The two channels of 8-bit PPG units operate independently. The PPG00 pin is connected to the ch0 PPG output, while the PPG10 pin is connected to the ch1 PPG output. r 8-bit prescaler + 8-bit PPG mode ch0 is used as an 8-bit prescaler while the count in ch1 is based on borrow outputs from ch0. Thus, 8-bit PPG waveforms can be output with arbitrary length of cycle time. The PPG00 pin is connected to the ch0 prescaler output, while the PPG10 pin is connected to the ch1 PPG output. r 16-bit PPG 1ch mode ch0 and ch1 are connected and used as a single 16-bit PPG. The PPG00 and PPG10 pins are connected to the 16-bit PPG output. For the MB90590 Series, the output signal from the Channel 0 PPG is not connected to any external pin. 175
CHAPTER 14 8/16-BIT PPG s 8/16-bit PPG Output Operation In this block, the ch0 PPG is activated to start counting when '1' is written to bit 7 (PEN0) of the PPGC0 (PWM operation mode control) register. Similarly, the ch1 PPG is activated to start counting when '1' is written to bit 15 (PEN1) of the PPGC1 register. Once the operation has started, counting is terminated by writing '0' to bit 7 (PEN0) of PPGC0 or in bit 15 (PEN1) of PPGC1. Once the counting is terminated, the output is maintained at the L level. For the MB90590 Series, the output signal from the Channel 0 PPG is not connected to any external pin. In 8-bit prescaler + 8-bit PPG mode, do not set ch1 to be in operation while ch0 operation is stopped. In 16-bit PPG mode, ensure that bit 7 (PEN0) of PPGC0 register and bit 15 (PEN1) of PPGC1 register are started or stopped simultaneously. The figure below is a diagram of PPG output operation. During PPG operation, a pulse wave is continuously output at a frequency and duty ratio (the ratio of the H-level period of the pulse wave to the L-level period). PPG continues operation until stop is specified explicitly. Figure 14.4-1 PPG Output Operation, Output Waveform
PEN Output pin PPG T (Start) (L+1) T (H+1) L : PRLL value H : PRLH value T : Input from peripheral clock ( clock selection by PPGC) , /4, /16) or timer base counter (depending on the 2.Starts operation based on PEN (from Lside).
s Relationship Between 8/16-bit PPG Reload Value and Pulse Width The width of the output pulse is determined by adding 1 to the reload register value and multiplying it by the count clock cycle. Note that when the reload register value is 00H during 8bit PPG operation or 0000H during 16-bit PPG operation, the pulse width is equivalent to one count clock cycle. In addition, note that when the reload register value is FFH during 8-PPG operation, the pulse width is equivalent to 256 count clock cycles. When the reload register value is FFFFH during 16-bit PPG operation, the pulse width is equivalent to 65536 count clock cycles.
L : PRLL value P1=T Ph=T (L+1) (H+1) H : value T : Input clock cycle Ph : High pulse width Pl : Low pulse width
176
14.5 Selecting a Count Clock for 8/16-Bit PPG
14.5 Selecting a Count Clock for 8/16-Bit PPG
The count clock used for the operation is supplied from the peripheral clock or the time base timer. The count clock can be selected from six choices.
s Selecting a Count Clock for 8/16-bit PPG Select ch0 clock at bit 4 to 2 (PCM2 to 0) of the PPG01 register, and ch1 clock at bit 7 to 5 (PCS2 to 0) of the PPG01 register. The clock is selected from a peripheral clock 1/16 to 1 times higher than a machine clock or an input clock from the time base timer. In 8-bit prescaler + 8-bit PPG mode or 16-bit PPG mode, however, the setting in the PCS2 to 0 has no effect. When the time base timer input is used, the first count cycle after a trigger or a stop may be shifted. The cycle may also be shifted if the time base counter is cleared during operation of this module. In 8-bit prescaler + 8-bit PPG mode, if ch1 is activated while ch0 is in operation and ch1 is stopped, the first count cycle may be shifted.
177
CHAPTER 14 8/16-BIT PPG
14.6 Controlling Pin Output of 8/16-bit PPG Pulses
The pulses generated by this module can be output from external pins PPG00 and PPG10.
s Controlling Pin Output of 8/16-bit PPG Pulses To output the pulses from an external pin, write '1' to the bit corresponding to each pin. When '0' is written to these bits (default), the pulses are not output from the corresponding external pins; the pins work as general-purpose ports. In 16-bit PPG mode, the same waveform is output from PPG00 and PPG10. Thus, the same output can be obtained by enabling both external pin. In 8-bit prescaler + 8-bit PPG mode, the 8-bit prescaler toggle output waveform is output from PPG00, while the 8-bit PPG waveform is output from PPG10. Figure 14.6-1 is a diagram of output waveforms in this mode. For the MB90590 Series, the output signal from the Channel 0 PPG is not connected to any external pin. Figure 14.6-1 8+8 PPG Output Operation Waveform
Ph0 PPG0 Pl0
PPG1
Ph1
Pl1
L0 : L1 : H1 : T : Ph0 : Pl0 : Ph1 : Pl1 :
ch0 PRLL value and ch0 PRLH value ch1 PRLL value ch1 PRLH value Input clock cycle PPG00 and 01 high pulse width PPG00 and 01 low pulse width PPG10 and 11 high pulse width PPG10 and 11 low pulse width
Pl0 = T Ph0 = T Pl1 = T Ph1 = T
(L0+1) (L0+1) (L0+1) (L0+1) (Ll+1) (Hl+1)
Note: Set the same value in ch0 PRLL and ch0 PRLH.
178
14.7 8/16-bit PPG Interrupts
14.7 8/16-bit PPG Interrupts
For the 8/16-bit PPG, an interrupt becomes active when the reload value counts out and a borrow occurs.
s 8/16-bit PPG Interrupts In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a borrow in each counter. In 16-bit PPG mode, PUG0 and PUF1 are simultaneously set by a borrow in the 16-bit counter. Therefore, enable only PIE0 or PIE1 to unify the interrupt causes. In addition, simultaneously clear the interrupt flags for PUF0 and PUF1.
179
CHAPTER 14 8/16-BIT PPG
14.8 Initial Values of 8/16-bit PPG Hardware
The hardware components of this block are initialized to the following values when reset:
s Initial Values of 8/16-bit PPG Hardware
r * * * PPGC0 -> 0X000001B PPGC1 -> 00000001B PPG10 -> XXXXXX00B
r * * * * PPG00 -> 'L' PPG10 -> 'L' PE00 PE10 -> -> PPG00 output disabled PPG10 output disabled
r * * IRQ0 -> 'L' IRQ1 -> 'L'
Hardware components other than the above are not initialized. Note: In a mode other than 16-bit PPG mode, it is recommended to use a word transfer instruction to write data in reload registers PRLL and PRLH. If two byte transfer instructions are used to write a data item to these registers, a pulse of unexpected cycle time may be output depending on the timing. Figure 14.8-1 Write Timing for 8/16-bit PPG Reload Registers (PRLL and PRLH)
PPG0 B A A B C B C D C D
x
Assume that PRLL is updated from A to C before point 1 in the time chart above, and PRLH is updated from B to D after point 1. Since the PRL values at point 1 are PRLL=C and PRLH=B, a pulse of L side count value C and H side count value B is output only once. Similarly, to write data in PRL of ch0 and ch1 in 16-bit PPG mode, use a long word transfer instruction, or use word transfer instructions in the order of ch0 and then ch1. In this mode, the data is only temporarily written to ch0 PRL. Then, the data is actually written into ch0 PRL when the ch1 PRL is written to. In a mode other than 16-bit PPG mode, ch0 and ch1 PRL are written independently.
180
14.8 Initial Values of 8/16-bit PPG Hardware Figure 14.8-2 PRL Write Operation Block Diagram
ch0 PRL write data ch1 PRL write data
Transferred in synchronization with ch1 write in 16-bit Temporary latch PPG mode ch0 write in a mode other than 16-bit PPG mode ch0 PRL ch1 write ch1 PRL
181
CHAPTER 14 8/16-BIT PPG
182
CHAPTER 15
DTP/EXTERNAL INTERRUPTS
This chapter explains the functions and operations of the DTP/external interrupts. 15.1 Outline of DTP/External Interrupts 15.2 DTP/External Interrupt Registers 15.3 Operations of DTP/External Interrupts 15.4 Switching Between External Interrupt and DTP Requests 15.5 Notes on Using DTP/External Interrupts
183
CHAPTER 15 DTP/EXTERNAL INTERRUPTS
15.1 Outline of DTP/External Interrupts
The data transfer peripheral (DTP) is located between an external peripheral and the F2MC-16LX CPU. The DTP receives a DMA request or interrupt request from the external peripheral, transfers the request to the F2MC-16LX CPU to activate the intelligent I/O service or interrupt processing.
s Outline of DTP/External Interrupts For the intelligent I/O service, 'H' and 'L' request levels are available. For an external interrupt request, four request levels are available: 'H,' 'L,' rising edge, and falling edge. For the MB90590 Series, the external bus interface is not supported. Therefore the DTP/ External Interrupt can not serve as the data transfer peripheral. It can be only used as the External Interrupt. For MB90V590, there are only four external pins assigned to this block. Therefor the external interrupt channel 4 to 7 are not supported. These external interrupts should be disabled. s Block Diagram of DTP/External Interrupts
Figure 15.1-1 Block Diagram of DTP/External Interrupts
8
Interrupt/DTP enable register
8
Gate
Cause F/F
Edge detection circuit
8
Request input
8
Interrupt/DTP cause register
16
Request level setting register
184
15.1 Outline of DTP/External Interrupts s DTP/external Interrupts Registers
bit
Address : 000030H
7 EN7 15 ER7 7 LB3 15 LB7
6 EN6 14 ER6 6 LA3 14 LA7
5 EN5 13 ER5 5 LB2 13 LB6
4 EN4 12 ER4 4 LA2 12 LA6
3 EN3 11 ER3 3 LB1 11 LB5
2 EN2 10 ER2 2 LA1 10 LA5
1 EN1 9 ER1 1 LB0 9 LB4
0 EN0 (ENIR) 8 ER0 (EIRR) 0 LA0 8 LA4
Request level setting register (ELVR) Request level setting register (ELVR) Interrupt/DTP cause register Interrupt/DTP enable register
bit
Address : 000031H
bit
Address : 000032H
bit
Address : 000033H
185
CHAPTER 15 DTP/EXTERNAL INTERRUPTS
15.2 DTP/External Interrupt Registers
The DTP/external interrupts has the following three types of registers: * Interrupt/DTP enable register (ENIR: Interrupt request enable register) * Interrupt/DTP flag (EIRR: External interrupt request register) * Request level setting register (ELVR: External level register)
s Interrupt/DTP Enable Register (ENIR: Interrupt request enable register)
7 ENIR Address : 000030H EN7 R/W
6 EN6 R/W
5 EN5 R/W
4 EN4 R/W
3 EN3 R/W
2 EN2 R/W
1 EN1 R/W
0 EN0 R/W
Initial value 00000000B
ENIR enables the function to issue a request to the interrupt controller using a device pin as an external interrupt/DTP request input. A pin corresponding to a '1' bit of this register is used as an external interrupt/DTP request input. A pin corresponding to a '0' bit holds the external interrupt/ DTP request input cause, but does not issue a request to the interrupt controller. s Interrupt/DTP Flags (EIRR: External interrupt request register)
15 EIRR Address : 000031H ER7 R/W
14 ER6 R/W
13 ER5 R/W
12 ER4 R/W
11 ER3 R/W
10 ER2 R/W
9 ER1 R/W
8 ER0
Initial value XXXXXXXX B for R and W.
R/W ........The objects differ
The EIRR indicates the presence of external interrupt/DTP requests at the pins corresponding to the '1' bits of this register. Writing '0' to a bit of this register clears the corresponding request flag. Writing '1' has no effect. '1' is always read from this register by a read-modify-write instruction.
186
15.2 DTP/External Interrupt Registers s Request Level Setting Register (ELVR: External level register)
7 Address : 000032 H LB3 R/W 7 Address : 000033 H LB7 R/W
6 LA3 R/W 6 LA7 R/W
5 LB2 R/W 5 LB6 R/W
4 LA2 R/W 4 LA6 R/W
3 LB1 R/W 3 LB5 R/W
2 LA1 R/W 2 LA5 R/W
1 LB0 R/W 1 LB4 R/W
0 LA0 R/W 0 LA4 R/W
Initial value 00000000B
Initial value 00000000B
ELVR defines the request event at the external pin. Each pin is assigned two bits as described in Table 15.2-1. If a request is detected by the input level, the interrupt flag is set as long as the input is at the specified level even after the flag is reset by software. Table 15.2-1 Interrupt Request Detection Factor for LBx and LAx Pins LBx 0 0 1 1 LAx 0 1 0 1 Interrupt request detection factor L level pin input H level pin input Rising edge pin input Falling edge pin input
187
CHAPTER 15 DTP/EXTERNAL INTERRUPTS
15.3 Operations of DTP/External Interrupts
When the interrupt flag is set, this block signals an interrupt to the interrupt controller. The interrupt controller judges the priority levels of the simultaneous interrupts, and issues an interrupt request to the F2MC-16LX CPU if the interrupt from this block has the highest priority. The F2MC-16LX CPU compares the ILM bits of its internal CCR register and the interrupt request. If the interrupt level of the request is higher than that indicated by the ILM bits, the F2MC-16LX CPU activates the hardware interrupt processing microprogram as soon as the currently executing instruction is terminated.
s External Interrupt Operation In the hardware interrupt processing microprogram, the CPU reads the ISE bit information from the interrupt controller, identifies that the request is for interrupt processing based on that information, and branches to the interrupt processing microprogram. The interrupt processing microprogram reads the interrupt vector area and issues an interrupt acknowledgment signal for the interrupt controller. Then, the microprogram transfers the jump destination address of the macro instruction generated from the vector to the program counter, and executes the user interrupt processing program. Figure 15.3-1 External Interrupt
External interrupt/DTP
Other request
Interrupt controller ICRyy
CMP
F2MC-16CPU IL
CMP
ELVR EIRR ENIR Cause
ICRxx
ILM NTA
188
15.3 Operations of DTP/External Interrupts s DTP operation To activate the intelligent I/O service, the user program initially sets the address of a register, assigned between 000000H and 0000FFH, in the I/O address pointer of the intelligent I/O service descriptor. Then, the user program sets the start address of the memory buffer in the buffer address pointer. The DTP operation sequence is almost the same as for external interrupts. The operation is identical until the CPU activates the hardware interrupt processing microprogram. Then, for the DTP, control is transferred to the intelligent I/O service processing microprogram, since the ISE bit read by the CPU within the hardware interrupt processing microprogram indicates the DTP. Once the intelligent I/O service is activated, a read or write signal is sent to the addresses external peripheral, and data is transferred between the peripheral and the chip. The external peripheral must cancel the interrupt request to this chip within three machine cycles after the transfer is made. When the transfer is completed, the descriptor is updated, and the interrupt controller generates a signal that clears the transfer cause. Upon receiving the signal to clear the transfer cause, this resource clears the flip-flop holding the cause and prepares for the next request from the pin. For details of the intelligent I/O service processing, refer to the MB90700 Programming Manual. Figure 15.3-2 Timing to Cancel the External Interrupt at the End of DTP Operation
Internal operation Selecting and reading descriptor Edge request or H level request * When data is transferred from the I/O register to memory in the intelligent I/O service
Interrupt cause
Address bus pin Data bus pin Read signal Write signal
Read address Read data
Write address Write data

Cancel within three machine cycles.
Figure 15.3-3 Sample Interface to the External Peripheral
External peripheral Data, address bus Register
Internal bus
IRQ DTP
INT CORE MEMORY
Cancel within three machine cycles after transfer.
MB90590
189
CHAPTER 15 DTP/EXTERNAL INTERRUPTS
15.4 Switching between External Interrupt and DTP Requests
To switch between external interrupt and DTP requests, use the ISE bit in the ICR register corresponding to this block, which is in the interrupt controller. Each pin is individually assigned ICR. Thus, a pin is used for a DTP request if '1' is written to the ISE bit of the corresponding ICR, and is used for an external interrupt request if '0' is written to the bit.
s Switching Between External Interrupt and DTP Requests
Figure 15.4-1 Switching Between External Interrupt and DTP Requests
Interrupt controller ICR xx ICR yy 1 F2 MC-16 CPU Pin External interrupt/DTP 0
DTP External interrupt
190
15.5 Notes on Using DTP/External Interrupts
15.5 Notes on Using DTP/External Interrupts
Note carefully the following items when using DTP/external interrupts: * Conditions on the externally connected peripheral when DTP is used * Recovery from standby * External interrupt/DTP operation procedure * External interrupt request level
s Notes on Using DTP/External Interrupts
r Conditions on the externally connected peripheral when DTP is used DTP supports only external peripherals that automatically clear a request once a transfer is completed. The system must be designed so that a transfer request is canceled within three machine cycles (provisional) after transfer operation starts. Otherwise, this resource assumes that a transfer request is issued. r Recovery from standby To use an external interrupt to recover from the standby state in clock stop mode, use an H level request as an input request. A L level request may result in misoperation. If an edge request is used, recovery from the standby state in clock stop mode cannot be performed. r External interrupt/DTP operation procedure To set registers in the external interrupt/DTP, follow the steps below: 1. Disable the bits corresponding to the enable register. 2. Set the bits corresponding to the request level setting register. 3. Clear the bits corresponding to the cause register. 4. Enable the bits corresponding to the enable register. (Steps 3. and 4. can be simultaneously performed by word specification.) To set a register in this resource, ensure that the enable register is disabled. Before enabling the enable register, ensure that the cause register is cleared. Clearing the cause register prevents a false interrupt cause from being determined while registers are set or interrupts are enabled. r External interrupt request level To detect an edge for an edge request level, the pulse width must be at least three machine cycles. As shown in Figure 15.5-1, when the request input level is related to the level setting, a request that is input from an external device to the interrupt controller is kept active even if the request is later canceled because a cause hold circuit has been installed. To cancel the request to the interrupt controller, the cause hold circuit must be cleared as shown in Figure 15.5-2.
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CHAPTER 15 DTP/EXTERNAL INTERRUPTS Figure 15.5-1 Clearing the Cause Hold Circuit Upon Level Set
Level detection Interrupt cause Cause F/F (cause hold circuit) Enable gate To interrupt controller
The cause is kept held unless cleared.
Figure 15.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller While Interrupts are Enabled
Interrupt cause Interrupt request to the interrupt controller Set inactive when the cause F/F is cleared. H level
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CHAPTER 16
A/D Converter
This chapter explains the functions and operations of the A/D converter. 16.1 Features of A/D Converter 16.2 Block Diagram of A/D Converter 16.3 A/D Converter Registers 16.4 Operations of A/D Converter 16.5 Conversion Using EI2OS 16.6 Conversion Data Protection
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CHAPTER 16 A/D Converter
16.1 Features of A/D Converter
The A/D converter converts analog input voltages into digital values. The A/D converter has the following features:
s Features of A/D converter
r Conversion time: 26.3 s min. per channel (at 16 MHz machine clock) r RC sequential compare conversion with sample and hold circuit r 10-bit resolution r Analog input selected from eight channels by programming Single conversion mode: One channel is selected for conversion. Scan conversion mode: Voltages in multiple consecutive channels are converted. Up to eight channels can be programmed. Continuous conversion mode: Voltages at the specified channel are converted repeatedly. Stop conversion mode: Voltages at the specified channel are converted, then the system pauses and stands by for the next activation. (The conversion start points can be synchronized.) r Interrupt request At the end of A/D conversion, a relevant interrupt request can be issued to the CPU. This interrupt can be used to activate the EI2OS, which automatically transfers A/D conversion result to memory. This feature is suitable for continuous processing. r Selectable activation cause The activation can be done by software, external trigger (falling edge), or timer (rising edge).
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16.1 Features of A/D Converter s Analog Input Enable Register Always write '1' to the ADER bit corresponding to a pin used as analog input.
bit Address: 00001BH
15 ADE7 R/W
14 ADE6 R/W
13 ADE5 R/W
12 ADE4 R/W
11 ADE3 R/W
10 ADE2 R/W
9 ADE1 R/W
8 ADE0 R/W Initial value 11111111B
Port 6 pins are controlled as described below. 0: Port input/output mode 1: Analog input mode '1' is set upon a reset. s Input Impedance The sampling circuit of the A/D Converter can be represented with the equivalent circuit shown below.
3.12K ohm max. Analog input 30p F max. ADC
Driving impedance to an analog input should be lower than 15.5K ohm when the sampling time is set to 4s (ST=0 and ST0=0 at 16MHz machine clock). Otheriwse the conversion accuracy will be worsened. If this is the case, set the sampling time longer (ST1=1 and ST0=1) or add external capacitor in order to compensate the driving impedance.
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CHAPTER 16 A/D Converter
16.2 Block Diagram of A/D Converter
Figure 16.2-1 shows a block diagram of the A/D converter.
s Block Diagram of A/D Converter
Figure 16.2-1 Block Diagram of A/D Converter
AVCC AVR AVSS
D/A converter
MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Input circuit
Sequential compare register
Comparator
Sample and hold circuit
Decoder
Data register
ADCR0, 1
A/D control register 0 A/D control register 1 Activation by external trigger
ADCS0, 1
ADTG
Activation by timer 16-bit Reload Timer 1 Operation clock
Prescaler
196
Data bus
16.3 A/D Converter Registers
16.3 A/D Converter Registers
The A/D converter has the following two types of registers: * Control status resister * Data register
s A/D Converter Registers
Figure 16.3-1 A/D Converter Register Configuration
15 ADCS1 ADCR1 8SSR bit
8
7 ADCS0 ADCR0 8 bit
0
bit Address : 000034H bit Address : 00035 H bit Address : 000036H bit Address : 000037H
7 MD1 15 BUSY 7 D7 15 S10
6 MD0 14 INT 6 D6 14 ST1
5
4
3
2 ANE2 10 STS0 2 D2 10
1
0 Control status registers (ADCS0 and ADCS1)
ANS2 ANS1 ANS0 13 INTE 5 D5 13 ST0 12 PAUS 4 D4 12 CT1 11 STS1 3 D3 11 CT0
ANE1 ANE0 9 STRT 1 D1 9 D9 8 DA 0 D0 8 D8 Data registers (ADCR0 and ADCR1)
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CHAPTER 16 A/D Converter
16.3.1 Control Status Registers (ADCS0)
The control status register (ADCS0) controls the A/D converter and indicates the status. Do not rewrite ADCS0 during A/D conversion.
s Control Status Registers (ADCS0)
7 ADCS0 Address: 000034 H MD1 0 R/W
6 MD0 0 R/W
5 ANS2 0 R/W
4 ANS1 0 R/W
3 ANS0 0 R/W
2 ANE2 0 R/W
1 ANE1 0 R/W
0 ANE0 0 R/W Initial value Bit attribute
[bits 7 and 6] MD1 and MD0 (A/D converter mode set): Table 16.3-1 Operation Mode Setting MD1 0 0 1 1 r Single mode: A/D conversion is continuously performed from the channel specified with ANS2 to ANS0 to the channel specified with ANE2 to ANE0. The conversion stops once it has been done for all these channels. r Continuous mode: A/D conversion is repeatedly performed from the channel specified with ANS2 to ANS0 to the channel specified with ANE2 to ANE0. r Stop mode: A/D conversion is performed from the channel specified with ANS2 to ANS0 to the channel specified with ANE2 to ANE0, pausing for each channel. The A/D conversion is resumed upon an activation. Upon a reset, these bits are initialized to '00.' Note: When activated in the continuous or stop mode, A/D conversion continues until it is stopped by the BUSY bit. The conversion is stopped by writing '0' to the BUSY bit. Reactivation disabled in single mode, continuous mode, and stop mode applies to all kinds MD0 0 1 0 1 Operation mode Single mode. Reactivation during operation is allowed. Single mode. Reactivation during operation is not allowed. Continuous mode. Reactivation during operation is not allowed. Stop mode. Reactivation during operation is not allowed.
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16.3 A/D Converter Registers of activation by software, an external trigger, and a timer. [bits 5, 4, and 3] ANS2, ANS1, and ANS0 (Analog start channel set): Use these bits to specify the start channel for A/D conversion. When the A/D converter is activated, A/D conversion starts from the channel selected with these bits. ANS2 0 0 0 0 1 1 1 1 * Read During A/D conversion, the current conversion channel is read from these bits. If the system is stopped in the stop mode, the last conversion channel is read. * Upon a reset, these bits are initialized to '000.' [bits 2, 1, and 0] ANE2, ANE1, and ANE0 (Analog end channel set): Use these bits to set the A/D conversion end channel. ANS2 0 0 0 0 1 1 1 1 Note: When the same channel is written to ANE2 to ANE0 and ANS2 to ANS0, conversion is performed for one channel only (single conversion). In the continuous or stop mode, operation returns to the start channel specified in ANS2 to ANS0 after the conversion is completed for the channel specified in ANE2 to ANE0. If the ANS value is greater than the ANE value, conversion starts from the ANS channel. Then, once conversion is complete up to channel 7, operation returns to channel 0 and 199 ANS1 0 0 1 1 0 0 1 1 ANS0 0 1 0 1 0 1 0 1 End channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ANS1 0 0 1 1 0 0 1 1 ANS0 0 1 0 1 0 1 0 1 Start channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
CHAPTER 16 A/D Converter conversion is performed up to the ANE channel. Upon a reset, these bits are initialized to '000.' Example: ANS=6, ANE=3, single mode Conversion is performed in the following sequence: CH6, CH7, CH0, CH1, CH2, CH3
200
16.3 A/D Converter Registers
16.3.2 Control Status Register (ADCS1)
The control status register (ADCS1) controls the A/D converter and indicates the status.
s Control Status Register (ADCS1)
15 ADCS1 Address: 000035 H BUSY 0 R/W
14 INT 0 R/W
13 INTE 0 R/W
12 PAUS 0 R/W
11 STS1 0 R/W
10 STS0 0 R/W
9 STRT 0 W
8 DA 0 R/W Initial value Bit attribute
[bit 15] BUSY (busy flag and stop): - Read This bit indicates the A/D converter operation. This bit is set when A/D conversion starts and is cleared when the conversion ends. - Write Writing "0" to this bit during A/D conversion forces the conversion to terminate. The above feature is used for forced stop in continuous or stop mode. "1" cannot be written to the BUSY bit. With a read-modify-write (RMW) instruction, "1" is read from this bit. In single mode, this bit is cleared at the end of A/D conversion. In continuous or stop mode, this bit is not cleared until conversion is stopped by writing "0." This bit is initialized to "0" upon a reset. Do not perform a forced stop and activation by software simultaneously (BUSY = 0, STRT = 1). [bit 14] INT (Interrupt): This bit is set when conversion data is written to ADCR. An interrupt request is issued if this bit is set while bit 5 (INTE) is '1.' In addition, the EI2OS is activated if it is enabled. Writing '1' has no effect. This bit is cleared by writing '0' or by the EI2OS interrupt clear signal. Note: To clear this bit by writing '0,' ensure that A/D conversion is not in progress. This bit initialized to '0' upon a reset. [bit 13] INTE (Interrupt enable): This bit is used to enable or disable interrupts at the end of conversion. - 0: Interrupts are disabled. - 1: Interrupts are enabled. Set this bit when using the EI2OS. The EI2OS is activated when an interrupt request is 201
CHAPTER 16 A/D Converter issued. Upon a reset, this bit is initialized to '0.' [bit 12] PAUS (A/D conversion pause): This bit is set when the A/D conversion is paused. Only one register is available for storing the A/D conversion result. Therefore, unless the conversion results are transferred by the EI2OS, the result data would be continuously updated and destroyed in continuous conversion. To prevent the above condition, the system is designed so that a data register value must be transferred by the EI2OS before the next conversion data is saved. A/D conversion pauses during that period. A/D conversion is resumed at the end of transfer by the EI2OS. This register is valid only when the EI2OS is used. Note: For the conversion data protection function, see Section 16.4, "Operations." Upon a reset, this bit is initialized to '0.' [bits 11 and 10] STS1 and STS0 (Start source select): Upon a reset, these bits are initialized to '00.' These bits are used to select the A/D conversion activation source. STS1 0 0 1 1 STS0 0 1 0 1 Activation by software Activation by external pin trigger and software Activation by timer and software Activation by external pin trigger, timer, and software Function
In a mode allowing two or more activation factors, A/D conversion is activated by the souce that occures first. The activation source setting changes as soon as it is updated. Thus, take care when updating it during A/D conversion. Note: The external pin trigger is detected by the falling edge. If this bit is updated to external trigger activation while the external trigger input level is 'L,' A/D may be activated at once. When timer is selected, the 16-bit Reload Timer 1 is selected. [bit 9] STRT (Start): A/D conversion is activated when '1' is written to this bit. To reactivate A/D conversion, write '1' to this bit again. Upon a reset, this bit is initialized to '0.' In the stop mode, a reactivation during the operation is not supported. Check the BUSY bit before writing '1'. Do not perform a forced stop and activation by software simultaneously. (BUSY=0, STRT=1)
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16.3 A/D Converter Registers [bit 8] DA This is a test bit. Always write '0' to this bit.
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CHAPTER 16 A/D Converter
16.3.3 Data Registers (ADCR1 and ADCR0)
These registers are used to store the digital values produced as a result of the conversion. ADCR1 stores the most significant two bits of the conversion result, while ADCR0 stores the lower eight bits. These register values are updated each time conversion is completed. Usually, the final conversion value is stored in these bits.
s Data Registers (ADCR1 and ADCR0)
ADCR0 bit Address : 000036 H
7 D7 R
6 D6 R 14 ST1 W
5 D5 R 13 ST0 W
4 D4 R 12 CT1 W
3 D3 R 11 CT0 W
2 D2 R 10
1 D1 R 9 D9 R
0 D0 R 8 D8 R Initial value 000010XX Initial value XXXXXXXX
bit ADCR1 Address : 000037 H
15 S10 W
'0' is always read from the bits 10 to 15 of ADCR1. The conversion data protection function is available. See Section 2.7.4, "Operations." Ensure that no data is written to these registers during A/D conversion. [bits 15] S10 This bit specifies the resolution of the conversion. When it is set to "0", the 10-bit A/D convertion is performed. Otherwise the 8-bit A/D conversion is performed and the result is stored in the D7 to D0. Reading this bit always returns "0". [bits 14 and 13] ST1 and ST0 (Sampling time): ST1 0 0 1 1 ST0 0 1 0 1 Function 64 machine cycles (4s at 16MHz) Reserved Reserved 4096 machine cycles (256s at 16MHz)
These bits determins the duration of the voltage sampling time at the inuput. Reading these bits always returns "00".
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16.3 A/D Converter Registers [bits 12 and 11] CT1 and CT0 (Compare time): CT1 0 0 1 1 CT0 0 1 0 1 Function 176 machine cycles (22s at 8MHz) 352 machine cycles (22s at 16MHz) Reserved Reserved
These bits determins the duration of the compare operation time. Do not set to '00' unless the machine clock is 8MHz. Otherwise the conversion accuracy is not guranteed. Reading these bits always returns "00".
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CHAPTER 16 A/D Converter
16.4 Operations of A/D Converter
The A/D converter operates employs the sequential compare technique, and has a 10bit resolution. Since the A/D converter has only one register (16 bits) for storing the conversion result, the conversion data registers (ADCR0 and ADCR1) are updated each time conversion is completed. Thus, the A/D converter alone must not be used for the continuous conversion. Use the F2MC-16 intelligent I/O service (EI2OS) function to transfer converted data to memory while conversion is in progress. The operation modes are explained below.
s Single Mode In this mode, the converter sequentially converts the analog inputs specified with the ANS and ANE bits. The converter stops operation after the conversion is completed for the end channel specified with the ANE bits. If the start and end channels are the same (ANS=ANE), conversion is performed only for one channel. Example: ANS = 0 0 0 , ANE = 0 1 1 Start -> AN0 -> AN1 -> AN2 -> AN3 -> End
ANS = 0 1 0 , ANE = 0 1 0 Start -> AN2 -> End s Continuous Mode In this mode, the converter sequentially converts the analog inputs specified with the ANS and ANE bits. After the conversion is completed for the end channel specified with the ANE bits, conversion is repeated from the analog inputs of the ANS. If the start and end channels are the same (ANS=ANE), conversion for one channel is repeated. Example: ANS = 0 0 0 , ANE = 0 1 1 Start -> AN0 -> AN1 -> AN2 -> AN3 -> AN0 -> Repeat
ANS = 0 1 0 , ANE = 0 1 0 Start -> AN2 -> AN2 -> AN2 -> Repeat In continuous mode, conversion is repeated until '0' is written to the BUSY bit. (Writing '0' to the BUSY bit forces the operation to end.) If the operation is terminated forcibly, conversion stops before conversion is completed. (Upon a forced stop, the conversion register stores the last data that has been converted completely.) s Stop Mode In this mode, the converter sequentially converts the analog inputs specified with the ANS and 206
16.4 Operations of A/D Converter ANE bits, pausing each time conversion for one channel is completed. To release pausing, activate the converter again. After the conversion is completed for the end channel specified with the ANE bits, conversion is repeated from the analog inputs of the ANS. If the start and end channels are the same (ANS=ANE), conversion is performed only for one channel. Example: ANS = 0 0 0 , ANE = 0 1 1 Start -> AN0 -> End -> Restart -> AN1 -> End -> Restarte -> AN2 -> End -> -> Restart -> AN3 -> End -> Restart --->AN0 Repeat
ANS = 0 1 0 , ANE = 0 1 0 Start -> AN2 -> End -> Restart -> AN2 -> End -> Restarte -> AN2 Repeat
Only the activation sources specified with STS1 and STS0 are used. Using this mode, start of conversion can be synchronized with the activation source.
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CHAPTER 16 A/D Converter
16.5 Conversion Using EI2OS
Figure 16.5-1 shows the processing flow from the start of A/D conversion to the transfer of converted data (in continuous mode).
s Conversion Using EI2OS
Figure 16.5-1 A/D conversion processing flow from the start to converted data transfer (in continuous mode)
Starting A/D conversion
Sample and hold Starting EI2OS Conversion Transferring data
End of conversion
Interrupt processing
Issuing interrupt
Clearing interrupt
The portion indicated by the star (
) is determined according to the EI2 OS setting.
208
16.5 Conversion Using EI2OS
16.5.1 Starting EI2OS in Single Mode
Follow the steps below to start the EI2OS in single mode. * To terminate conversion after analog inputs AN1 to AN3 are converted * To transfer conversion data sequentially to addresses 200H to 206H * To start conversion by software * To use the highest interrupt level
s Starting EI2OS in Single Mode
Settings EI2OS setting
Sample program MOV ICR3 #08H
Function Specifies the highest interrupt level, EI2OS activation upon an interrupt, and the descriptor address. Specifies the transfer destination address of converted data.
MOV BAPL, #00H MOV BAPM, #02H MOV BAPH, #00H MOV ISCS, #08H
Specifies word data transfer. The transfer destination address is incremented after transfer. Data is transferred from I/O to memory. Transfer is terminated in response to a request from a resource.
MOV I / OA, #38H MOV DCT, #03H A/D converter setting MOV ADCS0 #0BH MOV ADCS1 #A2H Interrupt sequence RET EI2OS transfer is performed three times. This count is the same as the conversion count. Specifies single mode, start channel AN1, and end channel AN3. Specifies activation by software and start of A/D conversion. Specifies return from an interrupt.
ICR3: Interrupt control register BAPL: Buffer address pointer, low-order BAPM: Buffer address pointer, medium-order BAPH: Buffer address pointer, high-order ISCS: EI2OS status register I/OA: I/O address counter
209
CHAPTER 16 A/D Converter DCT : Data counter
Activation
AN1 AN2 AN3 End
Interrupt Interrupt Interrupt
EI2 OS transfer EI 2OS transfer EI 2OS transfer
Interrupt sequenc Parallel processing
210
16.5 Conversion Using EI2OS
16.5.2 Starting EI2OS in Continuous Mode
Follow the steps below to start the EI2OS in continuous mode. * To convert analog inputs AN3 to AN5 and obtain two conversion data items for each channel * To transfer conversion data sequentially to addresses 600H to 60CH * To start conversion by external edge input * To use the highest interrupt level
s Starting EI2OS in Continuous Mode
Settings EI2OS setting
Sample program MOV ICR3 #08H
Function Specifies the highest interrupt level, EI2OS activation upon an interrupt, and the descriptor address. Specifies the transfer destination address of converted data.
MOV BAPL, #00H MOV BAPM, #06H MOV BAPH, #00H MOV ISCS, #08H
Specifies word data transfer. The transfer destination address is incremented after transfer. Data is transferred from I/O to memory. Transfer is terminated in response to a request from a resource. Transfer source address EI2OS transfer is performed six times. Data is transferred for three channels x 2. Specifies continuous mode, start channel AN3, and end channel AN5. Specifies activation by external edge and start of A/D conversion. Specifies return from an interrupt.
MOV I / OA, #38H MOV DCT, #06H A/D converter setting MOV ADCS0 #9DH MOV ADCS1 #A4H Interrupt sequence MOV ADCS1 #00H RET ICR3 : Interrupt control register BAPL : Buffer address pointer, low-order BAPM : Buffer address pointer, medium-order BAPH : Buffer address pointer, high-order ISCS : EI2OS status register
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CHAPTER 16 A/D Converter I/OA : I/O address counter DCT : Data counter
Activation
AN3 AN4 AN5
Interrupt Interrupt Interrupt
EI2OS transfer EI2OS transfer EI2OS transfer After six transfers Interrupt sequenc End
212
16.5 Conversion Using EI2OS
16.5.3 Starting EI2OS in Stop Mode
Follow the steps below to start the EI2OS in stop mode. * To convert analog input AN3 12 times at fixed intervals * To transfer conversion data sequentially to addresses 600H to 618H * To start conversion by external edge input * To use the highest interrupt level
s Starting EI2OS in Stop Mode
Settings EI2OS setting
Sample program MOV ICR3 #08H
Function Specifies the highest interrupt level, EI2OS activation upon an interrupt, and the descriptor address. Specifies the transfer destination address of converted data.
MOV BAPL, #00H MOV BAPM, #06H MOV BAPH, #00H MOV ISCS, #08H
Specifies word data transfer. The transfer destination address is incremented after transfer. Data is transferred from I/O to memory. Transfer is terminated in response to a request from a resource. Transfer source address EI2OS transfer is performed 12 times. Specifies continuous mode, start channel AN3, and end channel AN3 (one-channel conversion). Specifies activation by external edge and start of A/D conversion. Specifies return from an interrupt.
MOV I / OA, #38H
MOV DCT, #0CH A/D converter setting MOV ADCS0 #DBH MOV ADCS1 #A4H
Interrupt sequence
MOV ADCS1 #00H RET
ICR3 : Interrupt control register BAPL : Buffer address pointer, low-order BAPM : Buffer address pointer, medium-order BAPH : Buffer address pointer, high-order ISCS : EI2OS status register I/OA : I/O address counter 213
CHAPTER 16 A/D Converter DCT : Data counter
Activation
AN3 Interrupt EI2OS transfer Stop Activation by external edge
After 12 transfers
Interrupt sequenc End
214
16.6 Conversion Data Protection
16.6 Conversion Data Protection
The A/D converter has a conversion data protection function that enables continuous conversion and preservation of multiple data items using EI2OS. Since there is only one conversion data register, its value is updated each time conversion is completed. Thus, continuous data conversion results in the loss of the previous data due to storage of the new data. To prevent this situation, the A/D converter pauses after conversion if the previous data item has not been transferred to memory by EI2OS. The converted data is not saved until the previous data is transferred to memory.
s Conversion Data Protection The pause is released after data is transferred to memory by EI2OS. If the previous data has been transferred to memory, the A/D converter continues operation without pausing. Note: This function is related to the INT and INTE bits of ADCS1. The data protection function operates only when interrupts are enabled (INTE=1). If interrupts are disabled (INTE=0), this function is disabled. Continuous A/D conversion results in loss of previous data, since the converted data items are saved to the register one after another. If EI2OS is not used while interrupts are enabled (INTE=1), the INT bit is not cleared. Thus, the data protection function works and the A/D converter pauses. In this case, clearing the INT bit in the interrupt sequence releases the pause. If the A/D converter is pausing during EI2OS operation, disabling interrupts may restart the A/D converter. In this case, the value in the conversion data register may be changed without being transferred. Restarting the A/D converter while it is pausing destroys the standby data.
215
CHAPTER 16 A/D Converter s Flow of Data Protection Function (When EI2OS is Used)
Setting EI 2OS
Starting continuous A/D conversion Ending first conversion Saving the result in the data register Ending second conversion
Starting EI2 OS NO Pausing A/D conversion YES End EI2OS? Starting EI 2OS NO
End EI 2 OS? YES
Saving the result in the data register Ending third conversion
Continued
Ending the last conversion
Starting EI 2 OS Interrupt routine
End
Stooping A/D conversion
s Notes on using the conversion data protection function To start the A/D converter upon an external trigger or internal timer, A/D activation factor bits STS1 and STS0 of the ADCS1 register are used. Ensure that the input values of the external trigger or internal timer are inactive. If the values are active, A/D conversion may start immediately. When setting STS1 and STS0, ensure that '1' (input) is specified for ADTG and '0' (output) is specified for the internal timer (timer 2).
216
CHAPTER 17
UART0
This chapter explains the UART0 functions and operations. 17.1 Feature of UART0 17.2 UART Block Diagram 17.3 UART Registers 17.4 UART0 Operation 17.5 Baud Rate 17.6 Internal and External Clock 17.7 Transfer Data Format 17.8 Parity Bit 17.9 Interrupt Generation and Flag Set Timings 17.10 UART0 Application Example
217
CHAPTER 17 UART0
17.1 Feature of UART0
The UART is a serial I/O port for asynchronous or CLK synchronous communication. The MB90590 Series contains three UART's. The follwoing sections only describe the functionality of the UART 0. The remaining UART's have the identical function and the register addresses should be found in the I/O map.
s Feature of UART0 UART0 has the follwoing features. * * * * * * * * * Full duplex double buffer Supports CLK synchronous and CLK asynchronous start-stop data transfer. Multiprocessor mode support (mode 2) Internally dedicated baud rate generator (12 types) Supports flexible baud rate setting using an external clock input or internal timer. Variable data length (7 to 9 bits, [no parity]; 6 to 8 bits [with parity]). Error detect function (framing, overrun, and parity) Interrupt function (receive and transmit interrupts)Error detect function (framing, overrun, and parity) NRZ type transfer format
218
17.2 UART Block Diagram
17.2 UART Block Diagram
Figure 17.2-1 shows a block diagram of the UART.
s UART Block Diagram
Figure 17.2-1 UART Block Diagram
CONTROL BUS Receive interrupt (to CPU) Dedicated baud rate clock Transmit clock 16-bit reload timer 0 Clock select circuit Receive clock SCK0 Transmit interrupt (to CPU)
SCK0 Receive control circuit Start bit detect circuit Transmit control circuit
SIN0
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity counter
Transmit parity counter
SOT0
Receive status evaluation circuit
Receive shifter Receive complete UIDR
Transmit shifter
Transmit start
UODR
Receive error indication signal for EI2OS (to CPU)
Data bus
UMC register
PEN SBL MC1 MC0 SMDE RFC SCKE SOE
USR register
RDRF ORFE PE TDRE RIE TIE RBF TBF
URD register
BCH RC3 RC2 RC1 RC0 BCH0 P D8
CONTROL BUS
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CHAPTER 17 UART0
17.3 UART Registers
The UART has the following four registers: * Serial mode control register * Status register * Input data register/output data register * Rate and data register
s UART Registers
Serial mode control register Address: ch0 000020H
7 PEN
6 SBL (R/W) (0) 13 PE (R) (0)
5 MC1 (R/W) (0) 12 TDRE (R) (1)
4 MC0 (R/W) (0) 11 RIE
3 SMDE (R/W) (0) 10 TIE
2 RFC (W) (1) 9 RBF (R) (0)
1 SCKE (R/W) (0) 8 TBF (R) (0)
0 SOE (R/W) (0)
Bit number UMC0
Read/write Initial value Status register Address: ch0 15 000021H
(R/W) (0) 14
Bit number USR0
RDRF (R) (0)
ORFE (R) (0)
Read/write Initial value Input data register/ Output data register Address: ch0 000022H
(R/W) (0)
(R/W) (0)
7 D7
6 D6 (R/W) (X) 14 RC3 (R/W) (0)
5 D5 (R/W) (X) 13 RC2 (R/W) (0)
4 D4 (R/W) (X) 12 RC1 (R/W) (0)
3 D3 (R/W) (X) 11 RC0 (R/W) (0)
2 D2 (R/W) (X) 10 BCH0 (R/W) (0) 9 P (R/W) (0)
1 D1 (R/W) (X) 8 D8 (R/W) (X)
0 D0 (R/W) (X)
Bit number UIDR0(read) UODR0(write)
Read/write Initial value Rate and data register Address: ch0 000023H 15
(R/W) (X)
Bit number URD0
BCH (R/W) (0)
Read/write Initial value
220
17.3 UART Registers
17.3.1 Serial Mode Control Register (UMC)
UMC specifies the operation mode of UART0. Set the operation mode while operation is halted. However, the RFC bit can be accessed during operation.
s Layout of Serial Mode Control Register (UMC)
Serial mode control register Address: ch0 000020H
7 PEN
6 SBL (R/W) (0) MC1
5 MC0 (R/W) (0)
4 SMDE (R/W) (0)
3 RFC (W) (1)
2 SCKE (R/W) (0)
1 SOE (R/W) (0)
0Bit number UMC0
Read/write Initial value
(R/W) (0)
(R/W) (0)
s Serial Mode Control Register (UMC) Contents [Bit 7] PEN (Parity enable) Specifies whether to add (for transmit) or detect (for receive) a parity bit in serial data I/O. Set to "0" in mode 2. 0: Do not use parity 1: Use parity [Bit 6] SBL (Stop bit length) Specifies the number of stop bits for transmit data. For receive data, the first stop bit only is recognized and any second stop bit is ignored. 0: 1 bit length 1: 2 bits length [Bits 5, 4] MC1, MC0 (Mode control) These bits control the length of the transferred data. Table 17.3-1 lists the four transfer modes (data lengths) selectable by these bits. Table 17.3-1 UART Operation Modes Mode 0 1 2*2 3 MC1 0 0 1 1 MC0 0 1 0 1 Data Length*1 7 (6) 8 (7) 8+1 9 (8)
*1: The figures enclosed in parentheses indicate the data length with parity. *2: Mode 2 is used when a number of slave CPUs are connected to a single host CPU. As the receive parity check function cannot be used, set PEN in the UMC register to "0" (see Section 17.4 "Operation" for details). The transmit data length is 9 bits and no parity bit can be added. 221
CHAPTER 17 UART0 [Bit 3] SMDE (Synchro mode enable) This bit selects the transfer method. 0:Start-stop CLK synchronous transfer (clocked synchronous transfer using start and stop bits.) 1:Start-stop CLK asynchronous transfer [Bit 2] RFC (Receiver flag clear) Writing "0" to this bit clears the RDRF, ORFE, and PE flags in the USR register. Writing "1" has no effect. Reading always returns "1". Note: When receive interrupts are enabled during UART0 operation, only write "0" to RFC when either RDRF, ORFE, or PE is "1". [Bit 1] SCKE (SCLK enable) Writing "1" to this bit in CLK synchronous mode switches the port pin to the UART0 serial clock output pin and outputs the synchronizing clock. Set to 0 in CLK asynchronous mode or external clock mode. 0: The pin functions as a general purpose I/O port and does not output the serial clock. The pin functions as the external clock input pin when the port is set to input mode (DDR=0) and RC3 to 0 are set to "1111". 1: The pin functions as the UART0 serial clock output pin. Note: The corresponding bit of the Port Direction register should be set to "1" when the port pin is used as the clock output. This is for UART0 only. [Bit 0] SOE (Serial output enable) Writing "1" to this bit switches the port pin to the UART0 serial data output pin and enables serial output. 0: The pin functions as a port pin and does not output serial data. 1: The pin functions as the UART0 serial data output pin (SOT). Note: The corresponding bit of the Port Direction register should be set to "1" when the port pin is used as the serial output. This is for UART0 only.
222
17.3 UART Registers
17.3.2 Status Register (USR)
USR indicates the current state of the UART0 port.
s Status Register (USR) Layout
Status register Address: ch0 000021H
15 RDRF (R) (0)
14 ORFE (R) (0)
13 PE (R) (0)
12 TDRE (R) (1)
11 RIE (R/W) (0)
10 TIE (R/W) (0)
9 RBF (R) (0)
8 TBF (R) (0)
Bit number USR0
Read/write Initial value
s Status Register (USR) Contents [Bit 15] RDRF (Receiver data register full) This flag indicates the state of the UIDR0 (input data register). The flag is set when the receive data is loaded into UIDR0. Reading UIDR0 or writing "0" to RFC in the UMC0 register clears the flag. If RIE is active, a receive interrupt request is generated when RDRF is set. 0: No data in UIDR0 1: Data present in UIDR0 [Bit 14] ORFE (Over-run/framing error) The flag is set when an overrun or framing error occurs in receiving. Writing "0" to RFC in the UMC0 register clears the flag. When this flag is set, the data in UIDR0 is invalid and the load from the receive shifter to UIDR0 is not performed. If RIE is active, a receive interrupt request is generated when ORFE is set. 0: No error 1: Error Table 17.3-2lists the UIDR0 states after receive completion by RDRF or ORFE. Table 17.3-2 UIDR State after Receive Completion RDRF 0 0 1 1 ORFE 0 1 0 1 Empty Framing error Valid data Overrun error UIDR0 Data State
The data in UIDR is invalid if an overrun or framing error has occurred. Next data can be received after clearing the flag(s).
223
CHAPTER 17 UART0 [Bit 13] PE (Parity error) The flag is set when a receive parity error occurs. Writing "0" to RFC in the UMC register clears the flag. When this flag is set, the data in UIDR0 is invalid and the load from the receive shifter to UIDR0 is not performed. If RIE is active, a receive interrupt request is generated when PE is set. 0: No parity error 1: Parity error [Bit 12] TDRE (Transmitter data register empty) This flag indicates the state of the UODR0 (output data register). Writing transmit data to the UODR0 register clears the flag. The flag is set when the data is loaded to the transmit shifter and the transmission is started. If TIE is active, a transmit interrupt request is generated when TDRE is set. 0: Data present in UODR0 1: No data in UODR0 [Bit 11] RIE (Receiver interrupt enable) Enables receive interrupt requests. 0: Disable interrupts. 1: Enable interrupts. [Bit 10] TIE (Transmitter interrupt enable) Enables transmit interrupt requests. A transmit interrupt is generated immediately if transmit interrupts are enabled when TDRE is "1". 0: Disable interrupts. 1: Enable interrupts. [Bit 9] RBF (Receiver busy flag) This flag indicates that UART0 is receiving input data. The flag is set when the start bit is detected and cleared when the stop bit is detected. 0: Receiver idle 1: Receiver busy [Bit 8] TBF (Transmitter busy flag) This flag indicates that UART0 is transmitting input data. The flag is set when transmit data is written to the UODR0 register and cleared when transmission completes. 0: Transmitter idle 1: Transmitter busy
224
17.3 UART Registers
17.3.3 Input Data Register (UIDR) and Output Data Register (UODR)
UIDR (input data register) is the serial data input register. UODR (output data register) is the serial data output register. The most significant two bits (D7 and D6) are ignored if the data length is 6 bits and the most significant bit (D7) is ignored if the data length is 7 bits. Write to UODR only when TDRE = "1" in the USR register. Read UIDR only when RDRF = "1" in the USR register.
s Input Data Register (UIDR) and Output Data Register (UODR)
Input data register/ Output data register Address: ch0 000022H
7 D7
6 D6 (R/W) (X)
5 D5 (R/W) (X)
4 D4 (R/W) (X)
3 D3 (R/W) (X)
2 D2 (R/W) (X)
1 D1 (R/W) (X)
0 D0 (R/W) (X)
Bit number UIDR0(read) UODR0(write)
Read/write Initial value
(R/W) (X)
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CHAPTER 17 UART0
17.3.4 Rate and Data Register (URD)
URD selects the data transfer speed (baud rate) for UART0. The register also holds the most significant bit (bit 8) of the data when the transmit data length is 9 bits. Set the baud rate and parity when UART0 is halted.
s Layout of Rate and Data Register (URD)
Rate and data register Address: ch0 000023H
15 BCH (R/W) (0)
14 RC3 (R/W) (0)
13 RC2 (R/W) (0)
12 RC1 (R/W) (0)
11 RC0 (R/W) (0)
10 BCH0 (R/W) (0)
9 P (R/W) (0)
8 D8 (R/W) (X)
Bit number URD0
Read/write Initial value
s Rate and Data Register (URD) Contents [Bits 15, 10] BCH, BCH0 (Baud rate clock change) Specifies the machine cycles for the baud rate clock (see Section 17.4 "Operation" for details). Table 17.3-3 Clock Input Selection BCH 0 0 1 1 Note: Do not set BCH and BCH0 to "00". [Bits 14 to 11] RC3, RC2, RC1, RC0 (Rate control) Selects the clock input for the UART0 port (see Section 17.4 "Operation" for details). Table 17.3-4 Clock Input Selection RC3 to RC0 "0000" to "1011" "1101" "1111" Clock Input Dedicated baud rate generator 16-bit Reload Timer 0 External clock BCH0 0 1 0 1 Divider ratio Divide by 4 Divide by 3 Divide by 5 Setting Example for Each Machine Cycle - Prohibited setting For a 16-MHz machine cycle: 16/4 = 4 MHz For a 12-MHz machine cycle: 12/3 = 4 MHz For a 10-MHz machine cycle: 10/5 = 2 MHz
226
17.3 UART Registers Note: Do not set the rate control bits to "1100" "1110". [Bit 9] P Sets even or odd parity when parity is active (PEN = "1"). 0: Even parity 1: Odd parity [Bit 8] D8 Holds the bit 8 of the transfer data in mode 2 or 3 (9-bit data length) and no parity. Treated as bit 8 of the UIDR0 register for reading. Treated as bit 8 of the UODR register for writing. The bit has no meaning in the other modes. Write to D8 only when TDRE = "1" in the USR0 register.
227
CHAPTER 17 UART0
17.4 UART0 Operation
Table 17.4-1 lists the operating modes for UART0. Set the UMC register to switch between modes.
s UART0 Operation Modes
Table 17.4-1 UART0 Operating Modes Mode 0 Off On 1 Off 2 3 Off 9 Off On 8 8+1 8 7 7 CLK asynchronous or CLK synchronous 1 bit or 2 bits Parity On Data Length 6 Clock Mode Length of Stop Bits*
*: The number of stop bits can only be set for transmission. The number of receive stop bits is always set to one. Do not set modes other than those listed above. UART0 does not operate if an invalid mode is set. Note: UART0 uses start-stop clock synchronous transfer. Therefore, a start and stop bit are added to the data even in clock synchronous transfer.
228
17.5 Baud Rate
17.5 Baud Rate
When the dedicated baud rate generator is used, the following two types of baud rates are available: * CLK synchronous baud rate * CLK asynchronous baud rate
s CLK Synchronous Baud Rate The five URD register bits: BCH, BCH0 and RC3, RC2, RC1 select the baud rate for CLK synchronous transfer. First select the machine clock divider ratio using BCH and BCH0. BCH BCH0 0 1 1 1 0 1 => => => Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz] Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz] Divide by 5 [For example, at 10 MHz: 10/5 = 2 MHz]
Then, set the division ratio for the clock selected above in RC3, RC2, and RC1. The following three settings are available for CLK synchronous transfer. Other settings are prohibited. RC3 0 0 1 RC2 1 1 0 RC1 0 1 0 => => => Divide by 2 [For example, at 4 MHz: 4/2 = 2.0 M (bps)] Divide by 4 [For example, at 4 MHz: 4/4 = 1.0 M (bps)] Divide by 8 [For example, at 4 MHz: 4/8 = 0.5 M (bps)] (At 2 MHz, the speed becomes half the above examples.) s CLK Asynchronous Baud Rate The six URD register bits: BCH, BCH0 and RC3, RC2, RC1, RC0 select the baud rate for CLK asynchronous transfer. First select the machine clock divider ratio using BCH and BCH0. BCH BCH0 0 1 1 1 0 1 => => => Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz] Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz] Divide by 5 [For example, at 10 MHz: 10/5 = 2 MHz]
Then, set the asynchronous transfer clock division ratio for the clock selected above in RC3, RC2, RC1, and RC0. The following settings are available.
229
CHAPTER 17 UART0
RC3 RC2 RC1 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 Divide by 8 x 2 Divide by 8 x 4 Divide by 8 x 8 Not divided Divide by 8 0 0 0 Divide by 8 x 1
RC0
12 MHz BCH/ 0=10 0.5 / 2M 10 MHz BCH/ 0=11 1 / 1M -
x
0 Divide by 12 1 Divide by 13 0 1
x
Prohibited setting Divide by 8
The above 12 baud rates can be selected. The following formula shows how to calculate the CLK synchronous baud rate.
Baud rate = Baud rate = Baud rate =
/4 2m-1 /3 2m-1 /5 2m-1
[bps] (machine cycle = 16 MHz) [bps] (machine cycle = 12 MHz) [bps] (machine cycle = 10 MHz)
where is a machine cycle and m is in decimal notation for RC3 to 1. Note: The above formula for m=0 or m=1 cannot be calculated. Data transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1%. The baud rate is the CLK synchronous baud rate divided by 8 x 13, 8 x 12, or 8. Table 17.5-1 shows examples for 16 MHz, 12 MHz, and 10 MHz machine cycles. However, do not use the settings marked as '_' in the table. Table 17.5-1 Baud Rate CLK asynchronous (s/Baud) 16 MHz RC RC RC RC 3210 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 BCH/ 0=01 26/ 38460 2/500000 48/ 20833 52/ 19230 96/10417 12 MHz BCH/ 0=10 26/ 38460 2/500000 48/ 20833 52/ 19230 96/10417 10 MHz BCH/ 0=11 48/ 20833 52/ 19230 4/250000 96/10417 104/ 9615 192/ 5208 CLK asynchron ous divider ratio 8 x 12 8 x 13 8 8 8 x 12 8 x 13 8 x 12 CLK synchronous (s/Baud) 16 MHz BCH/ 0=01 0.5 / 2M -
230
17.5 Baud Rate Table 17.5-1 Baud Rate (Continued) CLK asynchronous (s/Baud) 16 MHz RC RC RC RC 3210 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 BCH/ 0=01 104/ 9615 192/ 5208 208/ 4808 16/ 62500 12 MHz BCH/ 0=10 104/ 9615 192/ 5208 208/ 4808 16/ 62500 10 MHz BCH/ 0=11 208/ 4808 416/ 2404 32/ 31250 CLK asynchron ous divider ratio 8 x 13 8 x 12 8 x 13 8 8 CLK synchronous (s/Baud) 16 MHz BCH/ 0=01 1 / 1M 2 / 500K 12 MHz BCH/ 0=10 1 / 1M 2 / 500K 10 MHz BCH/ 0=11 2 / 500K 4 / 250K
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CHAPTER 17 UART0
17.6 Internal and External Clock
Setting RC3 to 0 to "1101" selects the clock signal from the 16-bit Reload Timer. Setting RC3 to 0 to "1111" selects the external clock.
s Internal and External Clock The CLK asynchronous baud rate is the CLK synchronous baud rate divided by 8. Also, data transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1% of the selected baud rate. Table 17.6-1 lists the baud rates when the internal timer is selected as the clock. The values in this table are calculated for a machine cycle of 7.3728 MHz. However, do not use the settings marked as '_' in the table.
Baud rate=
/X 8 x 2 (n+1)
[bps]
: Machine cycle X: Divider ratio for the count clock source for the internal timer n: Reload value (decimal)
Table 17.6-1 Baud Rate and Reload Value Reload Value X = 21 (divide machine cycle by 2) 2 5 11 23 47 95 191 383 767
Baud Rate 76800 38400 19200 9600 4800 2400 1200 600 300
X = 23 (divide machine cycle by 8) 2 5 11 23 47 95 191
The values in the table are the reload values (decimal) for reload count operation of the 16-bit Reload Timer.
232
17.7 Transfer Data Format
17.7 Transfer Data Format
UART0 only handles NRZ (non-return-to-zero) type data. Figure 17.7-1 shows the relationship between the transmit/receive clock and the data for CLK synchronous mode.
s Transfer Data Format
Figure 17.7-1 Transfer Data Format
SCK0
SIN0, SOT0 0 Start 1 LSB 0 1 1 0 0 1 0 MSB 1 1 Stop Depends D8 Stop on the mode.
The transferred data is 01001101B (mode 1) or 101001101B (mode 3).
As shown in Figure 17.7-1 "Transfer Data Format", the transfer data always starts with the start bit (L level data), the specified number of data bits are transmitted with the LSB first, then transmission ends with the stop bit ('H' level data). Always input a clock if external clock operation is selected. When an internal clock (the dedicated baud rate generator or 16-bit Reload Timer) is selected, the clock is output continuously. When using CLK synchronous transfer, do not start data transfer until the selected baud rate clock has stabilized (for two baud rate clock cycles). When using CLK asynchronous transfer, set the SCKE bit in the UMC0 register to "0" to disable clock output. The transfer data format of SIN0 and SOUT0 is the same as shown in Figure 17.71 "Transfer Data Format".
233
CHAPTER 17 UART0
17.8 Parity Bit
The P bit in the URD0 register specifies whether to use even or odd parity when parity is enabled. The PEN bit in the UMC0 register enables parity.
s Parity Bit Inputting the data shown in Figure 17.8-1 to SIN when even parity is set causes a receive parity error. Figure 17.8-1 also shows the data transmitted when sending 001101B with even parity and odd parity. Figure 17.8-1 Serial Data with Parity Enabled
SIN0 0 Start 1 LSB 0 1 1 0 0 MSB 0 (Parity) 1 Stop (Receive parity error occurs P = 0)
SOT0 0 Start 1 LSB 0 1 1 0 0 MSB 1 (Parity) 1 Stop
(Even parity transmission P = 0)
SOT0 0 Start 1 LSB 0 1 1 0 0 MSB 0 (Parity) 1 Stop
(Odd parity transmission P = 1)
234
17.9 Interrupt Generation and Flag Set Timings
17.9 Interrupt Generation and Flag Set Timings
UART0 has two interrupt causes and six flags. The two interrupt causes are the receive and transmit interrupts. The six flags are RDRF, ORFE, PE, TDRE, RBF, and TBF. For reception, the RDRF, ORFE, and PE flags request an interrupt. For transmission, the TDRE flag requests an interrupt.
s Set Timings of the Six Flags
r RDRF flag The RDRF flag is set when receive data is loaded into the UIDR register. The flag is cleared by writing "0" to RFC in the UMC register or by reading the UIDR0 register. r ORFE flag The ORFE flag is an overrun or framing error flag. The flag is set when a receive error occurs and is cleared by writing "0" to RFC in the UMC0 register. r PE flag The PE flag is a reception parity error flag. The flag is set when a receive parity error occurs and is cleared by writing "0" to RFC in the UMC0 register. Note that the parity detect function is not available in mode 2. r TDRE flag The TDRE flag is set when the UODR0 register becomes empty and is available for writing. The flag is cleared by writing to the UODR0 register. The above four flags (RDRF, ORFE, PE, and TDRE) trigger transmit or receive interrupts. r RBF and TBF flags The RBF and TBF flags indicate that reception or transmission is in progress. The RBF flag becomes active during reception, and the TBF flag becomes active during transmission.
235
CHAPTER 17 UART0
17.9.1 Flag Set Timings for a Receive Operation (in Mode 0, 1, or 3)
The RDRF, ORFE, and PE flags are set and an interrupt request to the CPU generated when the final stop bit is detected indicating the end of reception transfer. The data in UIDR0 is invalid when either the ORFE or PE bit is active.
s Flag set Timings for a Receive Operation (in Mode 0, 1, or 3) Figures 17.9-1, 17.9-2, and 17.9-3 show the set timings of the RDRF, ORFE, and PE flags respectively. Figure 17.9-1 RDRF Set Timing (Mode 0, 1, or 3)
Data RDRF Stop (Stop)
Receive interrupt
Figure 17.9-2 ORFE Set Timing (Mode 0, 1, or 3)
Data RDRF = 1 ORFE Stop Data RDRF = 0 ORFE Stop
Receive interrupt (Overrun error)
Receive interrupt (Framing error)
Figure 17.9-3 PE Set Timing (Mode 0, 1, or 3)
Data PE Stop (Stop)
Receive interrupt
236
17.9 Interrupt Generation and Flag Set Timings
17.9.2 Flag set timings for a receive operation (in mode 2)
The RDRF flag is set when the final stop bit is detected and reception transfer ends with the last data bit (D8) having the value "1". The ORFE flag is set when the final stop bit is detected, irrespective of the value of the last data bit (D8). The data in UIDR0 is invalid when the ORFE bit is active. The interrupt request to the CPU is generated when either of the flags are set (see Section 17.10 "Application Example" for details on using mode 2).
s Flag Set Timings for a Receive Operation (in Mode 2)
Figure 17.9-4 RDRF Set Timing (Mode 2)
Data RDRF D6 D7 D8 Stop (Stop)
Receive interrupt
Figure 17.9-5 ORFE Set Timing (Mode 2)
Data RDRF = 1 ORFE Receive interrupt (Overrun error) D7 D8 Stop Data RDRF = 0 ORFE Receive interrupt (Framing error) D7 D8 Stop
237
CHAPTER 17 UART0
17.9.3 Flag set Timings for a Transmit Operation
TDRE is set and an interrupt request to the CPU is generated when the data written in UODR0 register is transferred to the internal shift register and the next data can be written to UODR0.
s Flag Set Timings for a Transmit Operation
Figure 17.9-6 TDRE Set Timing (Mode 0)
UODR write TDRE Interrupt request to the CPU Transmit interrupt SOT0 output
ST D0 D1
D2 D3 D4
D5 D6 D7
SP
SP ST D0 D1
D2 D3
ST: Start bit
D0 to D7: Data bits
SP: Stop bit
238
17.9 Interrupt Generation and Flag Set Timings
17.9.4 Status Flag During Transmit and Receive Operation
RBF is set when the start bit is detected and cleared when a stop bit is detected. The receive data in UIDR0 at the RBF clear timing is not yet valid. The data in UIDR0 becomes valid at the RDRF set timing.
s Status Flag during Transmit and Receive Operation Figure 17.9-7 shows the relationship between the RBF and receive interrupt flag timing. Figure 17.9-7 RBF Set Timing (Mode 0)
SIN0 input ST D0 D1 D2 D3 D4 D5 D6 D7 SP
RBF RDRF, PE, ORFE
ST: Start bit
D0 to D7: Data bits
SP: Stop bit
Writing the transmission data to UODR0 sets TBF. TBF is cleared when transmission completes. Figure 17.9-8 TBF Set Timing (Mode 0)
UODR write
SOT0 output
ST D0 D1
D2 D3 D4
D5 D6 D7
SP
SP
TBF
ST: Start bit
D0 to D7: Data bits
SP: Stop bit
Note: Receive operation starts after releasing a reset unless the SIN input pin is fixed at "1". Therefore, before setting the mode, write "0" to RFC in the UMC0 register to clear any receive flags that have been set. Set the communication mode when the RBF and TBF flags in the USR0 register are "0". The data transmitted and received during mode setting cannot be guaranteed.
239
CHAPTER 17 UART0 s EI2OS (Extended intelligent I/O service) See the Section 3.7 "Extended intelligent I/O service (EI2OS)" for details on EI2OS.
240
17.10 UART0 Application Example
17.10 UART0 Application Example
Mode 2 is used when a number of slave CPUs are connected to a host CPU (see Figure 17.10-1.)
s Application Example
Figure 17.10-1 RBF Set Timing (mode 0)
SIN0 input ST D0 D1 D2 D3 D4 D5 D6 D7 SP
RBF RDRF, PE, ORFE
ST: Start bit
D0 to D7: Data bits
SP: Stop bit
As shown in Figure 17.10-2, communication starts with the host CPU transmitting address data. The ninth bit (D8) of the address data is set to "1". The address selects the slave CPU with which communication will be established. The selected slave CPU communicates with the host CPU using a protocol determined by the user. In normal data, D8 is set to "0". Unselected slave CPUs wait in standby until the next communication session starts. Figure 17.10-3 shows a flowchart of operation in this mode. Because the parity check function is not available in this mode, set the PEN bit in the UMC0 register to "0". Figure 17.10-2 Example System Configuration Using Mode 2
SOT0
SIN0 Host CPU SOT0 SIN0 SOT0 SIN0
Slave CPU #0
Slave CPU #1
241
CHAPTER 17 UART0 Figure 17.10-3 Communication Flowchart for Mode 2 Operation
(Host CPU)
Start
(Slave CPU)
Start
Set the transfer mode to 3
Set the transfer mode to 2
Set the slave CPU selection in D0 to D7. Set D8 to "1". Transfer the byte.
Receive a byte
Selected? Set D8 to "0" and perform communications
No
Yes Set the transfer mode to 3 and enable SOT0 output
End
Perform communications with the master CPU
Use the status flag to confirm transfer completion, then set the transfer mode to 2 and disable SOT0 output
242
CHAPTER 18
SERIAL I/O
This chapter explains the functions and operations of the serial I/O. 18.1 Outline of Serial I/O 18.2 Serial I/O Registers 18.3 Serial I/O Prescaler (CDCR) 18.4 Serial I/O Operation 18.5 Negative Clock Operation
243
CHAPTER 18 SERIAL I/O
18.1 Outline of Serial I/O
The serial I/O interface operates in two modes: * Internal shift clock mode: Data is transferred in synchronization with the internal clock. * External shift clock mode: Data is transferred in synchronization with the clock supplied via the external pin (SCK3). By manipulating the general-purpose port sharing the external pin (SCK3), data can also be transferred by a CPU instruction in this mode.
s Serial I/O Block Diagram This block is a serial I/O interface that allows data transfer using clock synchronization. The interface consists of a single eight-bit channel. Data can be transferred from the LSB or MSB. Figure 18.1-1 Extended Serial I/O Interface Block Diagram
Internal data bus
(MSB first) D7 to D0
D7 to D0 (LSB first) Transfer direction selection
SIN3 Read SDR (Serial data register) Write
SOT3
SCK3 C o n t ro l c i rc u i t Shift clock counter
Internal clock
2
1
0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE
SMD2 SMD1 SMD0
Interrupt request Internal data bus
244
18.2 Serial I/O Registers
18.2 Serial I/O Registers
The serial I/O has the following two registers: * Serial mode control status register (SMCS) * Serial data register (SDR)
s Serial I/O Resisters
15
14
13
12 SIE 4
11 SIR 3 MODE
10 BUSY 2 BDS 2 D2
9
8 Serial mode control status register (SMCS)
Address : 00002DH SMD2 SMD1 SMD0 7 Address : 00002CH 7 Address : 00002E H D7 6 D6 5 D5 6 5
STOP STRT 1 SOE 1 D1 0 SCOE 0 D0
4 D4
3 D3
Serial data register (SDR)
245
CHAPTER 18 SERIAL I/O
18.2.1 Serial Mode Control Status Register (SMCS)
The serial mode control status register (SMCS) controls the serial I/O transfer mode.
s Serial Mode Control Status Register (SMCS)
15 14 13 SMCS Address: 00002DH SMD2 SMD1 SMD0 R/W R/W R/W
12 SIE R/W
11 SIR R/W *1
10 BUSY R
9
8
Initial value 00000010 B
STOP STRT R/W R/W *2
SMCS Address: 00002CH
7
6
5
4
3 MODE R/W
2 BDS R/W
1 SOE R/W
0 SCOE R/W
Initial value ----0000
B
*1: Only '0' can be written. *2: Only '1' can be written. '0' is always read.
s Bit functions of Serial Mode Control Status Register (SMCS) [bit 3] Serial mode selection bit (MODE)
The serial mode selection bit is used to select the conditions to start the transfer operation from the stop state. This bit must not be updated during operation. Table 18.2-1 Setting the Serial Mode Selection Bit MODE 0 1 Operation Transfer starts when STRT=1. [Default] Transfer starts when the serial data register is read or written to.
This bit is initialized to a '0' upon a reset, and can be read or written to. To activate the intelligent I/O service, ensure that '1' is written to this bit. [bit 2] Bit direction select bit (BDS) When serial data is input or output, this bit determines from which bit data is to be transferred first, the least significant bit (LSB first) or the most significant bit (MSB first), as shown in Table 18.2-2. Table 18.2-2 Setting the Transfer Direction Selection Bit 0 1 Note: Specify the bit ordering before any data is written to SDR. 246 LSB first [default] MSB first
18.2 Serial I/O Registers [bit 1] Serial output enable bit (SOE: Serial out enable) This bit controls the output from the serial I/O output external pins (SOT1 and 2) as shown in Table 18.2-3. Table 18.2-3 Setting the Serial Output Enable Bit 0 1 General-purpose port pin [default] Serial data output
This bit is initialized to '0' upon a reset. This bit is readable and writable. [bit 0] Shift clock output enable bit (SCOE: SCK1 output enable) This bit controls the output from the shift clock I/O output external pins (SCK1 and 2) as shown in Table 18.2-4. Table 18.2-4 Setting the Shift Clock Output Enable Bit 0 1 General-purpose port pin, transfer for each instruction [default] Shift clock output pin
Ensure that '0' is written to this bit when data is transferred for each instruction in external shift clock mode. This bit is initialized to '0' upon a reset. This bit is readable and writable. [Bits 15, 14, and 13] Shift clock selection bits (SMD2, SMD1, SMD0: Serial shift clock mode) These bits are used to select the serial shift clock mode, as shown in Table 18.2-5. Table 18.2-5 Setting the Serial Shift Clock Mode SMD2 0 0 0 0 1 1 1 1 div 3 4 5 M1 1 1 1 SMD1 0 0 1 1 0 0 1 1 DIV3 1 1 1 SMD0 0 1 0 1 0 1 0 1 DIV2 1 1 0 DIV1 0 0 1 DIV0 1 0 1 =16MHz div=8 1 MHz 500 kHz 125 kHz 62.5 kHz 31.25 kHz =8MHz div=4 1 MHz 500 kHz 125 kHz 62.5 kHz 31.25 kHz =4MHz div=4 500 kHz 250 kHz 62.5 kHz 31.25 kHz 5.625 kHz
External shift clock mode Reserved Reserved Recommended machine cycle 6 MHz 8 MHz 10 MHz
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CHAPTER 18 SERIAL I/O
div 6 7 8
M1 1 1 1
DIV3 1 1 1
DIV2 0 0 0
DIV1 1 0 0
DIV0 0 1 0
Recommended machine cycle 12 MHz 14 MHz 16 MHz
Setting of the Serial I/O prescaler (CDCR) * For details, see 2.6.4 "Serial I/O Prescaler". These bits are initialized to '000' upon a reset. These bits must not be updated during data transfer. Five types of internal shift clock and an external shift clock are available. Do not set 110 or 111 in SMD2, SMD1, and SMD0 as these values are reserved. Shift operation can be performed for each instruction by specifying SCOE =0 during clock selection and by using the ports that share the SCK1 and SCK2 pins. [bit 12] Serial I/O interrupt enable bit (SIE: Serial I/O interrupt enable) This bit controls the serial I/O interrupt request as shown in Table 18.2-6. Table 18.2-6 Setting the Interrupt Request Enable Bit 0 1 Serial I/O interrupt disabled [initial value] Serial I/O interrupt enabled
This bit is initialized to '0' upon a reset. This bit is readable and writable. [bit 11] Serial I/O interrupt request bit (SIR: Serial I/O interrupt request) When serial data transfer is completed, '1' is set to this bit. If this bit is set while interrupts are enabled (SIE=1), an interrupt request is issued to the CPU. The clear condition varies with the MODE bit. When '0' is written to the MODE bit, the SIR bit is cleared by writing '0'. When '1' is written to the MODE bit, the SIR bit is cleared by reading or writing to SDR. When the system is reset or '1' is written to the STOP bit, the SIR bit is cleared regardless of the MODE bit value. Writing '1' to the SIR bit has no effect. '1' is always read by a read operation of a readmodify-write instruction. [bit 10] Transfer status bit (BUSY) The transfer status bit indicates whether serial transfer is being executed. Table 18.2-7 Setting the Transfer Status Bit BUSY 0 1 Operating Stopped, or standing by for serial data register R/W [default] Serial transfer
This bit is initialized to '0' upon a reset. This is a read-only bit. [bit 9] Stop bit (STOP) The stop bit forcibly terminates serial transfer. When '1' is written to this bit, the transfer is
248
18.2 Serial I/O Registers stopped. Table 18.2-8 Setting the Stop Bit STOP 0 1 Normal operation Transfer stop by STOP=1 [initial value] Operating
This bit is initialized to '1' upon a reset. This bit is readable and writable. [bit 8] Start bit (STRT: Start) The start bit activates serial transfer. Writing '1' to this bit starts the data transfer when the MODE bit is set to 0. When the MODE bit is set to 1 and the STRT bit is set to 1, writing the data into serial data register starts the transfer. Writing '1' is ignored while the system is performing serial transfer or standing by for a serial shift register read or write. Writing '0' has no effect.'0' is always read.
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CHAPTER 18 SERIAL I/O
18.2.2 Serial Shift Data Register (SDR)
This serial data register stores the serial I/O transfer data. During transfer, the SDR must not be read or written to.
s Serial Shift Data Register (SDR)
SDR Address : 00002EH
7 D7 R/W
6 D6 R/W
5 D5 R/W
4 D4 R/W
3 D3 R/W
2 D2 R/W
1 D1 R/W
0 D0 R/W Initial value XXH (undefined)
250
18.3 Serial I/O Prescaler (CDCR)
18.3 Serial I/O Prescaler (CDCR)
The Serial I/O Prescaler provides the shift clock for the Serial I/O. The operation clock for the Serial I/O is obtained by dividing the machine clock. The Serial I/O is designed so that a constant baud rate can be obtained for a variety of machine clocks by the user of the communication prescaler. The CDCR register controls the machine clock division.
s Serial I/O Prescaler (CDCR)
15 CDCR Address: 00006DH MD R/W
14
13
12
11 DIV3 R/W
10 DIV2 R/W
9 DIV1 R/W
8 DIV0 R/W
Initial value 0---1111B
[bit 15] MD (Machine clock divide mode select): This bit is used to control the operation of the communication prescaler. 0: The Serial I/O Prescaler is disabled. 1: The Serial I/O Prescaler is enabled. [bits 11, 10, 9, and 8] DIV3 to DIV0 (Divide 3 to 0): These bits are used to determine the machine clock division ratio. Table 18.3-1 Machine Clock Division Ratio DIV3 to 0 1101B 1100B 1011B 1010B 1001B 1000B Note: When the division ratio is changed, allow two cycles for the clock to stabilize before starting communication. Division ratio 3 4 5 6 7 8
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CHAPTER 18 SERIAL I/O
18.4 Serial I/O Operation
The extended serial I/O consists of the serial mode control status register (SMCS) and shift register (SDR), and is used for input and output of 8-bit serial data.
s Serial I/O Operation The bits in the shift register are serially output via the serial output pin (SOT1 pin) at the falling edge of the serial shift clock (external clock or internal clock). The bits are serially input to the shift register (SDR) via the serial input pin (SIN1 pin) at the rising edge of the serial shift clock. The shift direction (transfer from MSB or LSB) is specified by the direction specification bit (BDS) of the serial mode control status register (SMCS). At the end of serial data transfer, this block is stopped or stands by for a read or write of the data register according to the MODE bit of the serial mode control status register (SMCS). To start transfer from the stop or standby state, follow the procedure below. r To resume operation from the stop state, write '0' to the STOP bit and '1' to the STRT bit. (The STOP and STRT bits can be set simultaneously.) r To resume operation from the serial shift data register R/W standby state, read or write to the data register.
252
18.4 Serial I/O Operation
18.4.1 Shift Clock
There are two modes of shift clock: internal or external shift clock. These two modes are selected by setting the SMCS. To switch the modes, ensure that serial I/O transfer is stopped. To check whether the serial I/O transfer is stopped, read the BUSY bit.
s Internal Shift Clock Mode In internal shift clock mode, data transfer is based on the internal clock. As a synchronization timing output, a shift clock of 50% duty ratio can be output from the SCK pin. Data is transferred at one bit per clock. The transfer speed is expressed as follows:
Transfer speed (s)=
A /Internal clock machine cycle (Hz)
"A" is the division ratio indicated by the SMD bits of SMCS. The value can be 10, 20, 80, 160, or 320. s External Shift Clock Mode In external shift clock mode, the data transfer is based on the external clock supplied via the SCK3 pin. Data is transferred at one bit per clock. The transfer speed can be between DC and 1/(5 machine cycles). For example, the transfer speed can be up to 2 MHz when 1 machine cycle is equal to 0.1 ms. A data bit can also be transferred by software, which is enabled as described below. Select external shift clock mode, and write '0' to the SCOE bit of SMCS. Then, write '1' to the direction register for the port sharing the SCK3 pin, and place the port in output mode. Then, when '1' and '0' are written to the data register (PDR) of the port, the port value output via the SCK3 pin is fetched as the external clock and transfer starts. Ensure that the shift clock starts from 'H.' Note: The SMCS or SDR must not be written to during serial I/O operation.
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CHAPTER 18 SERIAL I/O
18.4.2 Serial I/O Operation
There are four serial I/O operation statuses: * STOP * Halt * SDR R/W standby * Transfer
s Serial I/O Operation
r STOP The STOP state is initiated upon RESET or when '1' is written to the STOP bit of SMCS. The shift counter is initialized, and '0' is written to SIR. To resume operation from the STOP state, write '0' to STOP and '1' to STRT. (These two bits can be written to simultaneously.) Since the STOP bit overrides the STRT bit, transfer cannot be started by writing '1' to STRT while '1' is written to STOP. r Halt When transfer is completed while the MODE bit is '0,' '0' is set to BUSY and '1' is set to SIR of the SMCS, the counter is initialized, and the system stops. To resume operation from the stop state, write '1' to STRT. r Serial data register R/W standby When transfer is completed while the MODE bit is '1,' '0' is set to BUSY and '1' is set to SIR of the SMCS, and the system enters the serial data register R/W standby state. If the interrupt enable flag is set, an interrupt signal is output from this block. To resume operation from R/W standby state, read or write to the serial data register. This sets the BUSY bit to '1' and starts data transfer. r Transfer '1' is set to the BUSY bit and serial transfer is being performed. According to the MODE bit, the halt state or R/W standby state comes next. Figures 18.4-1 is diagrams of the operation transitions.
254
18.4 Serial I/O Operation Figure 18.4-1 Extended I/O Serial Interface Operation Transitions
End of transfer STRT=0, BUSY=0 MODE=0 STOP=0 & STRT=1 MODE=0 & STOP=0 & END STOP=0 & STRT=0 Reset STOP STOP=1 STRT=0, BUSY=0
STOP=1
STOP=0 & STRT=1
STOP=1
Transfer MODE=1 & END & STOP=0 STRT=1, BUSY=1 SDR R/W & MODE=1
Serial data register R/W standby STRT=1, BUSY=0 MODE=1
Figure 18.4-2 Serial Data Register Read/write
Serial data
Data bus SOT3 SIN3 Data bus Read Write Interrupt output Read Write CPU
Extended I/O serial interface
y
x
Interrupt input Data bus Interrupt controller
1. If '1' is written to MODE, transfer ends according to the shift clock counter. The read/write standby state starts when '1' is written to SIR. If '1' is written to the SIE bit, an interrupt signal is generated. No interrupt signal is generated when SIE is inactive or transfer has been terminated by writing '1' to STOP. 2. Reading or writing to the serial data register clears the interrupt request and starts serial transfer.
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CHAPTER 18 SERIAL I/O
18.4.3 Shift Operation Start/Stop Timing
To start the shift operation, set the STOP bit to "0" and the STRT bit to "1" in SMCS. The system may stop the shift operation at the end of transfer or when "1" is set in the STOP bit. * Stop by STOP=1 -> The system stops with SIR=0 regardless of the MODE bit. * Stop by end of transfer -> The system stops with SIR=1 regardless of the MODE bit. Regardless of the MODE bit, the BUSY bit becomes '1' during serial transfer and becomes '0' during stop or R/W standby state. To check the transfer status, read this bit.
s Shift Operation Start/Stop Timing
r Internal shift clock mode (LSB first)
Figure 18.4-3 Shift Operation Start/Stop Timing (Internal Clock)
SCK3 (Transfer start) STRT BUSY SOT3 DO0 If MODE=0
'1' output (Transfer end)
DO7 (Data maintained)
r External shift clock mode (LSB first)
Figure 18.4-4 Shift Operation Start/Stop Timing (External Clock)
SCK3 (Transfer start) STRT BUSY SOT3 DO0 DO7 (Data maintained) If MODE=0 (Transfer end)
r External shift clock mode with instruction shift (LSB first)
256
18.4 Serial I/O Operation Figure 18.4-5 Shift Operation Start/Stop Timing (External Shift Clock Mode with Instruction Shift)
SCK3 STRT BUSY SOT3
SCK='0' in PDR
SCK='0' in PDR SCK='1' in PDR (Transfer end)
If MODE=0 DO6 DO7 (Data maintained)
* For an instruction shift, 'H' is output when '1' is written to the bit corresponding to SCK of PDR, and 'L' is output when '0' is written. (When SCOE=0 in external shift clock mode) r Stop by STOP=1 (LSB first, internal clock)
Figure 18.4-6 Stop Timing when '1' is Written to the STOP Bit
'1' output SCK3 (Transfer start) (Transfer stop)
STRT BUSY STOP SOT3 DO3
If MODE=0
DO4
DO5 (Data maintained)
Note: DO7 to DO0 indicate output data. During serial data transfer, data is output from the serial output pin (SOT2) at the falling edge of the shift clock, and input from the serial input pin (SIN) at the rising edge.
Figure 18.4-7 Serial Data I/O Shift Timing
r LSB first (When the BDS bit is '0')
SCK3 SIN3 SOT3 D10 DO0 D11 DO1
SIN Input
D12 D13 SOT Output DO2 DO3
D14 DO4
D15 DO5
D16 DO6
D17 DO7
r MSB first (When the BDS bit is '1')
SCK3 SIN3 SOT3 D17 DO7 D16 DO6 D15
SOT Output SIN Input
D14 DO4
D13 DO3
D12 DO2
D11 DO1
D10 DO0
DO5
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CHAPTER 18 SERIAL I/O
18.4.4 Interrupt Function of the Extended Serial I/O Interface
This block can issue an interrupt request to the CPU. At the end of data transfer, the SIR bit is set as an interrupt flag. When '1' is written to the interrupt enable bit (SIE bit) of SMCS, an interrupt request is issued to the CPU.
s Interrupt Function of the Extended Serial I/O Interface
Figure 18.4-8 Interrupt Signal Output Timing of the Extended Serial I/O Interface
SCK3 BUSY SIR SDR RD/WR SOT3 DO6 SIE=1
(Transfer end)
* When MODE=1
DO7 (Data is maintained.)
258
18.5 Negative Clock Operation
18.5 Negative Clock Operation
The MB90590 Series supports the negative clock operation of the Serial I/O. In this opearation, the shift clock signal is simply negated by a inverter. Therefore the definition of the shift clock signal in the preceeding sections of the Serial I/O is inversed from the logic low level to logic high level, from the negative edge to the positive edge and vise-versa. This is the same for both the serial clock input and output.
s Negative Clock Operation
SES Address : 00002FH
7
6
5
4
3
2
1
0 NEG R/W Initial value _______0B
Table 18.5-1 Setting the NEG Bit NEG 0 1 Normal operation [default] The shift clock signal is inverted Operation
259
CHAPTER 18 SERIAL I/O
260
CHAPTER 19
CAN CONTROLLER
This chapter explains the functions and operations of the CAN controller. 19.1 Features of CAN Controller 19.2 Block Diagram of CAN Controller 19.3 List of Overall Control Registers 19.4 List of Message Buffers (ID Registers) 19.5 List of Message Buffers (DLC Registers and Data Registers) 19.6 Classifying the CAN Controller Registers 19.7 Transmission of CAN Controller 19.8 Reception of CAN Controller 19.9 Reception Flowchart of CAN Controller 19.10 How to Use the CAN Controller 19.11 Procedure for Transmission by Message Buffer (x) 19.12 Procedure for Reception by Message Buffer (x) 19.13 Setting Configuration of Multi-level Message Buffer
261
CHAPTER 19 CAN CONTROLLER
19.1 Features of CAN Controller
The CAN controller is a module built into a 16-bit microcontroller (F2MC-16LX). The CAN (Controller Area Network) is the standard protocol for serial communication between automobile controllers and is widely used in industrial applications.
s Features of CAN Controller The CAN controller has the following features: r Conforms to CAN Specification Version 2.0 Part A and B Supports transmission/reception in standard frame and extended frame formats r Supports transmitting of data frames by receiving remote frames r 16 transmitting/receiving message buffers 29-bit ID and 8-byte data Multi-level message buffer configuration r Supports full-bit comparison, full-bit mask and partial bit mask filtering. Two acceptance mask registers in either standard frame format or extended frame formats r Bit rate programmable from 10 Kbits/s to 1 Mbits/s (when input clock is at 16 MHz)
262
19.2 Block Diagram of CAN Controller
19.2 Block Diagram of CAN Controller
Figure 19.2-1 shows a block diagram of the CAN controller.
s Block Diagram of CAN Controller
Figure 19.2-1 Block Diagram of CAN Controller
F2MC-16LX bus Clock PSC PR BTR PH RSJ TOE TS RS CSR HALT NIE NT NS1, 0 RTEC Error control Transmitting/receiving sequencer Node status change interrupt generation Node status change interrupt Bus state machine IDLE, INT, SUSPND, transmit, receive, ERR, OVRLD Prescaler 1 to 64 frequency division Bit timing generation TQ (Operating clock) SYNC, TSEG1, TSEG2
BVALR TBFx, clear
TREQR
Transmitting buffer x decision
TBFx
Data counter
Acceptance filter control
Error frame generation Overload frame generation
TDLC RDLC TBFx TCANR
IDSEL Output driver
BITER, STFER, CRCER, FRMER, ACKER
ARBLOST
TX
TRTRR Transmission shift register TBFx, set, clear Transmission complete interrupt generation TIER RBFx, set RCR Reception complete interrupt generation RBFx, TBFx, set, clear RRTRR RBFx, set ROVRR ARBLOST AMSR BITER AMR0 0 1 Acceptance filter Receiving buffer x decision ACKER FRMER Arbitration check Bit error check Acknowledgment error check Form error check PH1 IDSEL Reception complete interrupt RDLC Transmission complete interrupt TDLC CRC generation Stuffing
RFWTR
TCR
ACK generation
CRCER STFER
CRC generation/error check
RIER
Receive shift register
Destuffing/stuffing error check
AMR1 IDR0 to 15 DLCR0 to 15 DTR0 to 15 RAM RAM address generation RBFx
Input latch
RX
RBFx, TBFx, RDLC, TDLC, IDSEL
LEIR
263
CHAPTER 19 CAN CONTROLLER
19.3 List of Overall Control Registers
Table 19.3-1 lists overall control registers.
s List of Overall Control Registers
Table 19.3-1 List of Overall Control Registers Address Register CAN0 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 001C00H 001C01H 001C02H 001C03H 001C04H 001C05H 001C06H 001C07H CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 001D00H 001D01H 001D02H 001D03H 001D04H 001D05H 001D06H 001D07H Last event indicator register Receive/transmit error counter Bit timing register LEIR R/W -------- 000-0000 Transmit complete register Receive complete register Remote request receiving register Receive overrun register Receive interrupt enable register Control status register TCR R/W 00000000 00000000 Message buffer valid register Transmit request register Transmit cancel register Abbreviation Access Initial Value
BVALR
R/W
00000000 00000000
TREQR
R/W
00000000 00000000
TCANR
W
00000000 00000000
RCR
R/W
00000000 00000000
RRTRR
R/W
00000000 00000000
ROVRR
R/W
00000000 00000000
RIER
R/W
00000000 00000000
CSR
R/W, R
00---000 0----001
RTEC
R
00000000 00000000
BTR
R/W
-1111111 11111111
264
19.3 List of Overall Control Registers Table 19.3-1 List of Overall Control Registers (Continued) Address Register CAN0 001C08H 001C09H 001C0AH 001C0BH 001C0CH 001C0DH 001C0EH 001C0FH 001C10H 001C11H 001C12H 001C13H 001C14H 001C15H 001C16H 001C17H 001C18H 001C19H 001C1AH 001C1BH CAN1 001D08H 001D09H 001D0AH 001D0BH 001D0CH 001D0DH 001D0EH 001D0FH 001D10H 001D11H 001D12H 001D13H 001D14H 001D15H 001D16H 001D17H 001D18H 001D19H 001D1AH 001D1BH Acceptance mask register 1 AMR1 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX Acceptance mask register 0 AMR0 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXX Remote frame receive waiting register Transmit interrupt enable register RFWTR R/W XXXXXXXX XXXXXXXX Transmit RTR register TRTRR R/W 00000000 00000000 IDE register Abbreviation IDER Access Initial Value
R/W
XXXXXXXX XXXXXXXX
TIER
R/W
00000000 00000000
XXXXXXXX XXXXXXXX
265
CHAPTER 19 CAN CONTROLLER
19.4 List of Message Buffers (ID Registers)
Table 19.4-1 lists message buffers (ID registers).
s List of Message Buffers (ID registers)
Table 19.4-1 List of Message Buffers (ID Registers) Address Register CAN0 001A00H to 001A1FH 001A20H 001A21H 001A22H 001A23H 001A24H 001A25H 001A26H 001A27H 001A28H 001A29H 001A2AH 001A2BH 001A2CH 001A2DH 001A2EH 001A2FH 001A30H 001A31H 001A32H 001A33H CAN1 001B00H to 001B1FH 001B20H 001B21H 001B22H 001B23H 001B24H 001B25H 001B26H 001B27H 001B28H 001B29H 001B2AH 001B2BH 001B2CH 001B2DH 001B2EH 001B2FH 001B30H 001B31H 001B32H 001B33H ID register 4 IDR4 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 3 IDR3 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 2 IDR2 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 1 IDR1 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 0 IDR0 R/W XXXXX--- XXXXXXXX General-purpose RAM Abbrevia -tion Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX XXXXXXXX
--
R/W
266
19.4 List of Message Buffers (ID Registers) Table 19.4-1 List of Message Buffers (ID Registers) (Continued) Address Register CAN0 001A34H 001A35H 001A36H 001A37H 001A38H 001A39H 001A3AH 001A3BH 001A3CH 001A3DH 001A3EH 001A3FH 001A40H 001A41H 001A42H 001A43H 001A44H 001A45H 001A46H 001A47H 001A48H 001A49H 001A4AH 001A4BH 001A4CH 001A4DH 001A4EH 001A4FH CAN1 001B34H 001B35H 001B36H 001B37H 001B38H 001B39H 001B3AH 001B3BH 001B3CH 001B3DH 001B3EH 001B3FH 001B40H 001B41H ID register 8 001B42H XXXXX--- XXXXXXXX 001B43H 001B44H 001B45H 001B46H 001B47H 001B48H 001B49H 001B4AH 001B4BH 001B4CH 001B4DH 001B4EH 001B4FH ID register 11 IDR11 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 10 IDR10 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 9 IDR9 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX IDR8 R/W XXXXXXXX XXXXXXXX ID register 7 IDR7 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 6 IDR6 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 5 IDR5 R/W XXXXX--- XXXXXXXX Abbrevia -tion Access Initial Value
XXXXXXXX XXXXXXXX
267
CHAPTER 19 CAN CONTROLLER Table 19.4-1 List of Message Buffers (ID Registers) (Continued) Address Register CAN0 001A50H 001A51H 001A52H 001A53H 001A54H 001A55H 001A56H 001A57H 001A58H 001A59H 001A5AH 001A5BH 001A5CH 001A5DH 001A5EH 001A5FH CAN1 001B50H 001B51H 001B52H 001B53H 001B54H XXXXXXXX XXXXXXXX 001B55H ID register 13 001B56H 001B57H 001B58H 001B59H 001B5AH 001B5BH 001B5CH 001B5DH 001B5EH 001B5FH ID register 15 IDR15 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX ID register 14 IDR14 R/W XXXXX--- XXXXXXXX XXXXXXXX XXXXXXXX IDR13 R/W XXXXX--- XXXXXXXX ID register 12 IDR12 R/W XXXXX--- XXXXXXXX Abbrevia -tion Access Initial Value
XXXXXXXX XXXXXXXX
268
19.5 List of Message Buffers (DLC Registers and Data Registers)
19.5 List of Message Buffers (DLC Registers and Data Registers)
Table 19.5-1 lists message buffers (DLC registers), and Table 19.5-2 lists message buffers (data registers).
s List of Message Buffers (DLC Registers and Data Registers)
Table 19.5-1 List of Message Buffers (DLC Registers and Data Registers) Address Register CAN0 001A60H 001A61H 001A62H 001A63H 001A64H 001A65H 001A66H 001A67H 001A68H 001A69H 001A6AH 001A6BH 001A6CH 001A6DH 001A6EH 001A6FH 001A70H 001A71H 001A72H 001A73H 001A74H 001A75H CAN1 001B60H 001B61H 001B62H 001B63H 001B64H 001B65H 001B66H 001B67H 001B68H 001B69H 001B6AH 001B6BH 001B6CH 001B6DH 001B6EH 001B6FH 001B70H 001B71H 001B72H 001B73H 001B74H 001B75H DLC register 10 DLCR10 R/W ----XXXX DLC register 9 DLCR9 R/W ----XXXX DLC register 8 DLCR8 R/W ----XXXX DLC register 7 DLCR7 R/W ----XXXX DLC register 6 DLCR6 R/W ----XXXX DLC register 5 DLCR5 R/W ----XXXX DLC register 4 DLCR4 R/W ----XXXX DLC register 3 DLCR3 R/W ----XXXX DLC register 2 DLCR2 R/W ----XXXX DLC register 1 DLCR1 R/W ----XXXX DLC register 0 Abbrevia -tion DLCR0 Access Initial Value
R/W
----XXXX
269
CHAPTER 19 CAN CONTROLLER Table 19.5-1 List of Message Buffers (DLC Registers and Data Registers) (Continued) Address Register CAN0 001A76H 001A77H 001A78H 001A79H 001A7AH 001A7BH 001A7CH 001A7DH 001A7EH 001A7FH CAN1 001B76H 001B77H 001B78H 001B79H 001B7AH 001B7BH 001B7CH 001B7DH 001B7EH 001B7FH DLC register 15 DLCR15 R/W ----XXXX DLC register 14 DLCR14 R/W ----XXXX DLC register 13 DLCR13 R/W ----XXXX DLC register 12 DLCR12 R/W ----XXXX DLC register 11 Abbrevia -tion DLCR11 Access Initial Value
R/W
----XXXX
270
19.5 List of Message Buffers (DLC Registers and Data Registers) s List of Message Buffers (Data Registers)
Table 19.5-2 List of Message Buffers (Data Registers) Address Register CAN0 001A80H to 001A87H 001A88H to 001A8FH 001A90H to 001A97H 001A98H to 001A9FH 001AA0H to 001AA7H 001AA8H to 001AAFH 001AB0H to 001AB7H 001AB8H to 001ABFH 001AC0H to 001AC7H 001AC8H to 001ACFH 001AD0H to 001AD7H 001AD8H to 001ADFH 001AE0H to 001AE7H CAN1 001B80H to 001B87H 001B88H to 001B8FH 001B90H to 001B97H 001B98H to 001B9FH 001BA0H to 001BA7H 001BA8H to 001BAFH 001BB0H to 001BB7H 001BB8H to 001BBFH 001BC0H to 001BC7H 001BC8H to 001BCFH 001BD0H to 001BD7H 001BD8H to 001BDFH 001BE0H to 001BE7H Data register 0 (8 bytes) Abbrevia -tion Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX
DTR0
R/W
Data register 1 (8 bytes)
DTR1
R/W
Data register 2 (8 bytes)
DTR2
R/W
Data register 3 (8 bytes)
DTR3
R/W
Data register 4 (8 bytes)
DTR4
R/W
Data register 5 (8 bytes)
DTR5
R/W
Data register 6 (8 bytes)
DTR6
R/W
Data register 7 (8 bytes)
DTR7
R/W
Data register 8 (8 bytes)
DTR8
R/W
Data register 9 (8 bytes)
DTR9
R/W
Data register 10 (8 bytes) Data register 11 (8 bytes) Data register 12 (8 bytes)
DTR10
R/W
DTR11
R/W
DTR12
R/W
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CHAPTER 19 CAN CONTROLLER Table 19.5-2 List of Message Buffers (Data Registers) (Continued) Address Register CAN0 001AE8H to 001AEFH 001AF0H to 001AF7H 001AF8H to 001AFFH CAN1 001BE8H to 001BEFH 001BF0H to 001BF7H 001BF8H to 001BFFH Data register 13 (8 bytes) Data register 14 (8 bytes) Data register 15 (8 bytes) Abbrevia -tion Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX
DTR13
R/W
DTR14
R/W
DTR15
R/W
272
19.6 Classifying the CAN Controller Registers
19.6 Classifying the CAN Controller Registers
There are three types of CAN controller registers: * Overall control registers * Message buffer control registers * Message buffers
s Overall Control Registers The overall control registers are the following four registers: * * * * Control status register (CSR) Last event indicator register (LEIR) Receive and transmit error counter (RTEC) Bit timing register (BTR)
s Message Buffer Control Registers The message buffer control registers are the following 14 registers: * * * * * * * * * * * * * * Message buffer valid register (BVALR) IDE register (IDER) Transmission request register (TREQR) Transmission RTR register (TRTRR) Remote frame receiving wait register (RFWTR) Transmission cancel register (TCANR) Transmission complete register (TCR) Transmission interrupt enable register (TIER) Reception complete register (RCR) Remote request receiving register (RRTRR) Receive overrun register (ROVRR) Reception interrupt enable register (RIER) Acceptance mask select register (AMSR) Acceptance mask registers 0 and 1 (AMR0 and AMR1)
s Message Buffers The message buffers are the following three registers: * * * ID register x (x = 0 to 15) (IDRx) DLC register x (x = 0 to 15) (DLCRx) Data register x (x = 0 to 15) (DTRx)
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19.6.1 Control Status Register (CSR)
Control status register (CSR) is prohibited from executing any bit manipulation instructions (Read-Modify-Write instructions).
s Control Status Register (CSR)
15 Address: 001C01H (CAN0) 001D01H (CAN1) Read/write: Initial value: TS (R) (0)
14 RS (R) (0)
13 -- (--) (--)
12 -- (--) (--)
11 -- (--) (--)
10 NT (R/W) (0)
9 NS1 (R) (0)
8 NS0 (R) (0)
7 Address: 001C00H (CAN0) 001D00H (CAN1) Read/write : Initial value: TOE (R/W) (0)
6 -- (--) (--)
5 -- (--) (--)
4 -- (--) (--)
3 -- (--) (--)
2 NIE (R/W) (0)
1 Reserved (W) (0)
0 HALT (R/W) (1)
[Bit 15] TS: Transmit status bit This bit indicates whether a message is being transmitted. 0: Message not being transmitted 1: Message being transmitted This bit is 0 even while error and overload frames are transmitted. [Bit 14] RS: Receive status bit This bit indicates whether a message is being received. 0: Message not being received 1: Message being received While a message is on the bus, this bit becomes 1. Therefore, this bit is also 1 while a message is being transmitted. This bit does not necessarily indicates whether a receiving message passes through the acceptance filter. As a result, when this bit is 0, it implies that the bus operation is stopped (HALT = 0); the bus is in the intermission/bus idle or a error/overload frame is on the bus. [Bit 10] NT: Node status transition flag If the node status is changed to increment, or from Bus Off to Error Active, this bit is set to 1. In other words, the NT bit is set to 1 if the node status is changed from Error Active (00) to Warning (01), from Warning (01) to Error Passive (10), from Error Passive (10) to Bus Off (11), and from Bus Off (11) to Error Active (00). Numbers in parentheses indicate the values of NS1 and NS0 bits. 274
19.6 Classifying the CAN Controller Registers When the node status transition interrupt enable bit (NIE) is 1, an interrupt is generated. Writing 0 sets the NT bit to 0. Writing 1 to the NT bit is ignored. 1 is read when a Read Modify Write instruction is performed. [Bits 9 to 8] NS1 and NS0: Node status bits 1 and 0 These bits indicate the current node status. Table 19.6-1 Correspondence between NS1 and NS0 and Node Status NS1 0 0 1 1 Note: Warning (error active) is included in the error active in CAN Specification 2.0B for the node status, however, indicates that the transmit error counter or receive error counter has exceeded 96. The node status change diagram is shown in Figure 19.6-1. Figure 19.6-1 Node Status Transition Diagram
Hardware reset REC: Receive error counter TEC: Transmit error counter Error active REC >= 96 or TEC >= 96 REC < 96 and TEC < 96 Warning (Error active) REC >= 128 or TEC >= 128 REC < 128 and TEC < 128 Error passive TEC >= 256 Bus off (HALT = 1) After 0 has been written to the HALT bit of the register (CSR), continuous 11-bit High levels (recessive bits) are input 128 times to the receive input pin (RX).
NS0 0 1 0 1 Error active Warning (error active) Error passive Bus off
Node Status
[Bit 7] TOE: Transmit output enable bit Writing 1 to this bit switches from a general-purpose port pin to a transmit pin of the CAN controller. 0: General-purpose port pin 1: Transmit pin of CAN controller [Bit 2] NIE: Node status transition interrupt enable bit This bit enables or disables a node status transition interrupt (when NT = 1).
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CHAPTER 19 CAN CONTROLLER 0: Node status transition interrupt disabled 1: Node status transition interrupt enabled [Bit 1] Reserved The is a reserved bit. Do not write "1" to this bit. [Bit 0] HALT: Bus operation stop bit This bit sets or cancels bus operation stop, or displays its state.
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19.6 Classifying the CAN Controller Registers
19.6.2 Bus Operation Stop Bit (HALT = 1)
The bus operation stop bit sets or cancels stopping of bus operation, or indicates its status
s Conditions for Setting Bus Operation Stop (HALT=1) There are three conditions for setting bus operation stop (HALT = 1): * * * After hardware reset When node status changed to bus off By writing 1 to HALT
Note: The bus operation should be stopped by writing 1 to HALT before the F2MC-16LX is changed in low-power consumption mode (stop mode, timer mode, and hardware stand-by mode). If transmission is in progress when 1 is written to HALT, the bus operation is stopped (HALT = 1) after transmission is terminated. If reception is in progress when 1 is written to HALT, the bus operation is stopped immediately (HALT = 1). If received messages are being stored in the message buffer (x), stop the bus operation (HALT = 1) after storing the messages. To check whether the bus operation has stopped, always read the HALT bit. s Conditions for Canceling Bus Operation Stop (HALT = 0) * By writing 0 to HALT
Note: Canceling the bus operation stop after hardware reset or by writing 1 to HALT as above conditions is performed after 0 is written to HALF and continuous 11-bit High levels (recessive bits) have been input to the receive input pin (RX) (HALT = 0). Canceling the bus operation stop when the node status is changed to bus off as above conditions is performed after 0 is written to HALF and continuous 11-bit High levels (recessive bits) have been input 128 times to the receive input pin (RX) (HALT = 0). Then, the values of both transmit and receive error counters reach 0 and the node status is changed to error active. s State during Bus Operation Stop (HALT = 1) * * * The bus does not perform any operation, such as transmission and reception. The transmit output pin (TX) outputs a High level (recessive bit). The values of other registers and error counters are not changed.
Note: The bit timing register (BTR) should be set during bus operation stop (HALT = 1).
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CHAPTER 19 CAN CONTROLLER
19.6.3 Last Event Indicator Register (LEIR)
This register indicates the last event. The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event is set to 1, other bits are set to 0s.
s Last Event Indicator Register (LEIR)
7 Address: 001C02H (CAN0) 001D02H (CAN1) Read/write : Initial value: NTE (R/W) (0)
6 TCE (R/W) (0)
5 RCE (R/W) (0)
4 -- (--) (--)
3 MBP3 (R/W) (0)
2 MBP2 (R/W) (0)
1 MBP1 (R/W) (0)
0 MBP0 (R/W) (0)
[Bit 7] NTE: Node status transition event bit When this bit is 1, node status transition is the last event. This bit is set to 1 at the same time the NT bit of the control status register (CSR) is set. This bit is also set to 1 irrespective of the setting of the node status transition interrupt enable bit (NIE) of CSR. Writing 0 to this bit sets the NTE bit to 0. Writing 1 to this bit is ignored. 1 is read when a Read Modify Write instruction is executed. [Bit 6] TCE: Transmit completion event bit When this bit is 1, it indicates that transmit completion is the last event. This bit is set to 1 at the same time as any one of the bits of the transmit completion register (TCR). This bit is also set to 1, irrespective of the settings of the bits of the transmit interrupt enable register (TIER). Writing 0 sets this bit to 0. Writing 1 to this bit is ignored. 1 is read when a Read Modify Write instruction is performed. When this bit is set to 1, the MBP3 to MBP0 bits are used to indicate the message buffer number completing the transmit operation. [Bit 5] RCE: Receive completion event bit When this bit is 1, it indicates that receive completion is the last event. This bit is set to 1 at the same time as any one of the bits of the receive complete register (RCR). This bit is also set to 1 irrespective of the settings of the bits of the receive interrupt enable register (RIER). Writing 0 sets this bit to 0. Writing 1 to this bit is ignored. 1 is read when a Read Modify Write instruction is performed. When this bit is set to 1, the MBP3 to MBP0 bits are used to indicate the message buffer number completing the receive operation.
278
19.6 Classifying the CAN Controller Registers [Bits 3 to 0] MBP3 to MBP0: Message buffer pointer bits When the TCE or RCE bit is set to 1, these bits indicate the corresponding numbers of the message buffers (0 to 15). If the NTE bit is set to 1, these bits have no meaning. Writing 0 sets these bits to 0s. Writing 1 to these bits is ignored. 1s are read when a Read Modify Write instruction is performed. If LEIR is accessed within an CAN interrupt handler, the event causing the interrupt is not neccessarily the same as indicated by LEIR. In the time from interrupt request to the LEIR access by the interrupt handler there may occur other CAN events.
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CHAPTER 19 CAN CONTROLLER
19.6.4 Receive and Transmit Error Counters (RTEC)
The receive and transmit error counters indicate the counts for transmission errors and reception errors defined in the CAN specifications. These registers can only be read.
s Receive and Transmit Error Counters (RTEC)
15 Address: 001C05H (CAN0) 001D05H (CAN1) Read/write: Initial value: TEC7 (R) (0)
14 TEC6 (R) (0)
13 TEC5 (R) (0)
12 TEC4 (R) (0)
11 TEC3 (R) (0)
10 TEC2 (R) (0)
9 TEC1 (R) (0)
8 TEC0 (R) (0)
7 Address: 001C04H (CAN0) 001D04H (CAN1) Read/write: Initial value: REC7 (R) (0)
6 REC6 (R) (0)
5 REC5 (R) (0)
4 REC4 (R) (0)
3 REC3 (R) (0)
2 REC2 (R) (0)
1 REC1 (R) (0)
0 REC0 (R) (0)
[Bits 15 to 8] TEC7 to TEC0: Transmit error counter These are transmit error counters. TEC7 to TEC0 values indicate 0 to 7 when the counter value is more than 256, and the subsequent increment is not counted for counter value. In this case, Error Passive is indicated for the node status (NS1 and NS0 of control status register CSR = 11). [Bits 7 to 0] REC7 to REC0: Receive error counter These are receive error counters. REC7 to REC0 values indicate 0 to 7 when the counter value is more than 256, and the subsequent increment is not counted for counter value. In this case, Bus Off is indicated for the node status (NS1 and NS0 of control status register CSR = 10).
280
19.6 Classifying the CAN Controller Registers
19.6.5 Bit Timing Register (BTR)
Bit timing register (BTR) stores the prescaler and bit timing setting.
s Bit Timing Register (BTR)
15 Address: 001C07H (CAN0) 001D07H (CAN1) Read/write: Initial value: -- (--) (--)
14 TS2.2 (R/W) (1)
13 TS2.1 (R/W) (1)
12 TS2.0 (R/W) (1)
11 TS1.3 (R/W) (1)
10 TS1.2 (R/W) (1)
9 TS1.1 (R/W) (1)
8 TS1.0 (R/W) (1)
7 Address: 001C06H (CAN0) 001D06H (CAN1) Read/write: Initial value: RSJ1 (R/W) (1)
6 RSJ0 (R/W) (1)
5 PSC5 (R/W) (1)
4 PSC4 (R/W) (1)
3 PSC3 (R/W) (1)
2 PSC2 (R/W) (1)
1 PSC1 (R/W) (1)
0 PSC0 (R/W) (1)
Note This register should be set during bus operation stop (HALT = 1). [Bits 14 to 12] TS2.2 to TS2.0: Time segment 2 setting bits 2 to 0 These bits define the number of the time quanta (TQ's) for the time segment 2 (TSEG2). The time segment 2 is equal to the phase buffer segment 2 (PHASE_SEG2) in the CAN specification. [Bits 11 to 8] TS1.3 to TS1.0: Time segment 1 setting bits 3 to 0 These bits define the number of the time quanta (TQ's) for the time segment 1 (TSEG1). The time segment 1 is equal to the propagation segment (PROP_SEG) + phase buffer segment 1 (PHASE_SEG1) in the CAN specification. [Bits 7 and 6] RSJ1 and RSJ0: Resynchronization jump width setting bits 1 and 0 These bits define the number of the time quanta (TQ's) for the resynchronization jump width. [Bits 5 to 0] PSC5 to PSC0: Prescaler setting bits 5 to 0 These bits define the time quanta (TQ) of the CAN controller. The bit time segments defined in the CAN specification, and the CAN controller are shown in Figures 19.6-2 and 19.6-3 respectively.
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CHAPTER 19 CAN CONTROLLER Figure 19.6-2 Bit Time Segment in CAN Specification
Nominal bit time SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2
Sample point
Figure 19.6-3 Bit Time Segment in CAN Controller
Nominal bit time SYNC_SEG TSEG1 TSEG2
Sample point
The relationship between PSC = PSC5 to PSC0, TSI = TS1.3 to TS1.0, TS2 = TS2.2 to TS1.0, and RSJ = RSJ1 and RSJ0 when the input clock (CLK), time quanta (TQ), bit time (BT), synchronous segment (SYNC_SEG), time segment 1 and 2 (TSEG1 and TSEG2), and resynchronization jump width [(RSJ1 and RSJ0) +1] frequency division is shown below. The input clock is supplied with the machine clock. TQ BT = (PSC + 1) x CLK = SYNC_SEG + TSEG1 + TSEG2 (1 + (TS1 + 1) + (TS2 + 1)) x TQ = (3 + TS1 + TS2) TQ RSJW = (RSJ + 1) x TQ For correct operation, the following conditions should be met. BT >= 8TQ
TSEG2 >= RSJW + 2TQ*1 TSEG1 >= delay time*2 + RSJW *1) 2TQ: Data processing time *2) Delay time: Twice as long as the sum of the bus propagation, input comparator and output driver delay
282
19.6 Classifying the CAN Controller Registers
19.6.6 Message Buffer Valid Register (BVALR)
Message buffer valid register (BVALR) stores the validity of the message buffers or displays their state.
s Message Buffer Valid Register (BVALR)
15 Address: 000071H (CAN0) 000081H (CAN1) Read/write: Initial value: BVAL15 (R/W) (0)
14 BVAL14 (R/W) (0)
13 BVAL13 (R/W) (0)
12 BVAL12 (R/W) (0)
11 BVAL11 (R/W) (0)
10 BVAL10 (R/W) (0)
9 BVAL9 (R/W) (0)
8 BVAL8 (R/W) (0)
7 Address: 000070H (CAN0) 000080H (CAN1) Read/write: Initial value: BVAL7 (R/W) (0)
6 BVAL6 (R/W) (0)
5 BVAL5 (R/W) (0)
4 BVAL4 (R/W) (0)
3 BVAL3 (R/W) (0)
2 BVAL2 (R/W) (0)
1 BVAL1 (R/W) (0)
0 BVAL0 (R/W) (0)
0: Message buffer (x) invalid 1: Message buffer (x) valid If the message buffer (x) is set to invalid, it will not transmit or receive messages. If the buffer is set to invalid during transmission operating, it becomes invalid (BVALx = 0) after the transmission is completed or terminated by an error. If the buffer is set to invalid during reception operating, it immediately becomes invalid (BVALx = 0). If received messages are stored in a message buffer (x), the message buffer (x) is invalid after storing the messages. Note: x indicates a message buffer number (x = 0 to 15). When invaliding a message buffer (x) by writing 0 to a bit (BVALx), execution of a bit manipulation instruction is prohibited until the bit is set to 0.
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CHAPTER 19 CAN CONTROLLER
19.6.7 IDE register (IDER)
This register stores the frame format used by the message buffers (x) during transmission/reception.
s IDE Register (IDER)
15 Address: 001C09H (CAN0) 001D09H (CAN1) Read/write: Initial value: IDE15 (R/W) (X)
14 IDE14 (R/W) (X)
13 IDE13 (R/W) (X)
12 IDE12 (R/W) (X)
11 IDE11 (R/W) (X)
10 IDE10 (R/W) (X)
9 IDE9 (R/W) (X)
8 IDE8 (R/W) (X)
7 Address: 001C08H (CAN0) 001D08H (CAN1) Read/write: Initial value: IDE7 (R/W) (X)
6 IDE6 (R/W) (X)
5 IDE5 (R/W) (X)
4 IDE4 (R/W) (X)
3 IDE3 (R/W) (X)
2 IDE2 (R/W) (X)
1 IDE1 (R/W) (X)
0 IDE0 (R/W) (X)
0: The standard frame format (ID11 bit) is used for the message buffer (x). 1: The extended frame format (ID29 bit) is used for the message buffer (x). Note: This register should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) = 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored.
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19.6 Classifying the CAN Controller Registers
19.6.8 Transmission Request Register (TREQR)
Transmission request register (TREQR) stores transmission requests to the message buffers (x) or displays their state.
s Transmission Request Register (TREQR)
15 Address: 000073H (CAN0) 000083H (CAN1) Read/write: Initial value: TREQ15 (R/W) (0) 7 Address: 000072H (CAN0) 000082H (CAN1) Read/write: Initial value: TREQ7 (R/W) (0)
14 TREQ14 (R/W) (0) 6 TREQ6 (R/W) (0)
13 TREQ13 (R/W) (0) 5 TREQ5 (R/W) (0)
12 TREQ12 (R/W) (0) 4 TREQ4 (R/W) (0)
11 TREQ11 (R/W) (0) 3 TREQ3 (R/W) (0)
10 TREQ10 (R/W) (0) 2 TREQ2 (R/W) (0)
9 TREQ9 (R/W) (0) 1 TREQ1 (R/W) (0)
8 TREQ8 (R/W) (0) 0 TREQ0 (R/W) (0)
When 1 is written to TREQx, transmission to the message buffer (x) starts. If RFWTx of the remote frame receiving wait register (RFWTR)*1 is 0, transmission starts immediately. However, if RFWTx = 1, transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR)*1 becomes 1). Transmission starts*2 immediately even when RFWTx = 1, if RRTRx is already 1 when 1 is written to TREQx. *1: For RFWTR and TRTRR, see 19.6.9 and 19.6.10. *2: For cancellation of transmission, see 19.6.11 and 19.6.12. Writing 0 to TREQx is ignored. 0 is read when a Read Modify Write instruction is performed. If clearing (to 0) at completion of the transmit operation and setting by writing 1 are concurrent, clearing is preferred. If 1 is written to more than one bit, transmission is performed, starting with the lower-numbered message buffer (x). TREQx is 1 while transmission is pending, and becomes 0 when transmission is completed or canceled.
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CHAPTER 19 CAN CONTROLLER
19.6.9 Transmission RTR Register (TRTRR)
This register stores the RTR (Remote Transmission Request) bits for the message buffers (x).
s Transmission RTR Register (TRTRR)
15 Address: 001C0BH (CAN0) 001D0BH (CAN1) Read/write: Initial value: TRTR15 (R/W) (0)
14 TRTR14 (R/W) (0)
13 TRTR13 (R/W) (0)
12 TRTR12 (R/W) (0)
11 TRTR11 (R/W) (0)
10 TRTR10 (R/W) (0)
9 TRTR9 (R/W) (0)
8 TRTR8 (R/W) (0)
7 Address: 001C0AH (CAN0) 001D0AH (CAN1) Read/write: Initial value: TRTR7 (R/W) (0)
6 TRTR6 (R/W) (0)
5 TRTR5 (R/W) (0)
4 TRTR4 (R/W) (0)
3 TRTR3 (R/W) (0)
2 TRTR2 (R/W) (0)
1 TRTR1 (R/W) (0)
0 TRTR0 (R/W) (0)
0: Data frame 1: Remote frame
286
19.6 Classifying the CAN Controller Registers
19.6.10 Remote Frame Receiving Wait Register (RFWTR)
Remote frame receiving wait register (RFWTR) stores the conditions for starting transmission when a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is 1 and TRTRx of the transmitting RTR register (TRTRR) is 0). * 0: Transmission starts immediately * 1: Transmission starts after waiting until remote frame received (RRTRx of remote request receiving register (RRTRR) becomes 1)
s Remote Frame Receiving Wait Register (RFWTR)
15 Address: 001C0DH (CAN0) 001D0DH (CAN1) Read/write: Initial value: RFWT15 (R/W) (X)
14 RFWT14 (R/W) (X)
13 RFWT13 (R/W) (X)
12 RFWT12 (R/W) (X)
11 RFWT11 (R/W) (X)
10 RFWT10 (R/W) (X)
9 RFWT9 (R/W) (X)
8 RFWT8 (R/W) (X)
7 Address: 001C0CH (CAN0) 001D0CH (CAN1) Read/write: Initial value: RFWT7 (R/W) (X)
6 RFWT6 (R/W) (X)
5 RFWT5 (R/W) (X)
4 RFWT4 (R/W) (X)
3 RFWT3 (R/W) (X)
2 RFWT2 (R/W) (X)
1 RFWT1 (R/W) (X)
0 RFWT0 (R/W) (X)
Note: Transmission starts immediately if RRTRx is already 1 when a request for transmission is set. For remote frame transmission, do not set RFWTx to 1.
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19.6.11 Transmission Cancel Register (TCANR)
When 1 is written to TCANx, this register cancels a pending request for transmission to the message buffer (x). At completion of cancellation, TREQx of the transmission request register (TREQR) becomes 0. Writing 0 to TCANx is ignored. This is a write-only register and its read value is always 0.
s Transmission Cancel Register (TCANR)
15 Address: 000075H (CAN0) 000085H (CAN1) Read/write: Initial value: TCAN15 (W) (0)
14 TCAN14 (W) (0)
13 TCAN13 (W) (0)
12 TCAN12 (W) (0)
11 TCAN11 (W) (0)
10 TCAN10 (W) (0)
9 TCAN9 (W) (0)
8 TCAN8 (W) (0)
7 Address: 000074H (CAN0) 000084H (CAN1) Read/write: Initial value: TCAN7 (W) (0)
6 TCAN6 (W) (0)
5 TCAN5 (W) (0)
4 TCAN4 (W) (0)
3 TCAN3 (W) (0)
2 TCAN2 (W) (0)
1 TCAN1 (W) (0)
0 TCAN0 (W) (0)
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19.6 Classifying the CAN Controller Registers
19.6.12 Transmission Complete Register (TCR)
At completion of transmission by the message buffer (x), the corresponding TCx becomes 1. If TIEx of the transmission complete interrupt enable register (TIER) is 1, an interrupt occurs.
s Transmission Complete Register (TCR)
15 Address: 000077H (CAN0) 000087H (CAN1) Read/write: Initial value: TC15 (R/W) (0)
14 TC14 (R/W) (0)
13 TC13 (R/W) (0)
12 TC12 (R/W) (0)
11 TC11 (R/W) (0)
10 TC10 (R/W) (0)
9 TC9 (R/W) (0)
8 TC8 (R/W) (0)
7 Address: 000076H (CAN0) 000086H (CAN1) Read/write: Initial value: TC7 (R/W) (0)
6 TC6 (R/W) (0)
5 TC5 (R/W) (0)
4 TC4 (R/W) (0)
3 TC3 (R/W) (0)
2 TC2 (R/W) (0)
1 TC1 (R/W) (0)
0 TC0 (R/W) (0)
r Conditions for TCx = 0 * * Write 0 to TCx. Write 1 to TREQx of the transmission request register (TREQR).
After the completion of transmission, write 0 to TCx to set it to 0. Writing 1 to TCx is ignored. 1 is read when a Read Modify Write instruction is performed. Note: If setting to 1 by completion of the transmit operation and clearing to 0 by writing occur at the same time, the bit is set to 1.
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19.6.13 Transmission Interrupt Enable Register (TIER)
This register enables or disables the transmission interrupt by the message buffer (x). The transmission interrupt is generated at transmission completion (when TCx of the transmission complete register (TCR) is 1).
s Transmission Interrupt Enable Register (TIER)
15 Address: 001C0FH (CAN0) 001D0FH (CAN1) Read/write: Initial value: TIE15 (R/W) (0)
14 TIE14 (R/W) (0)
13 TIE13 (R/W) (0)
12 TIE12 (R/W) (0)
11 TIE11 (R/W) (0)
10 TIE10 (R/W) (0)
9 TIE9 (R/W) (0)
8 TIE8 (R/W) (0)
7 Address: 001C0EH (CAN0) 001D0EH (CAN1) Read/write: Initial value: TIE7 (R/W) (0)
6 TIE6 (R/W) (0)
5 TIE5 (R/W) (0)
4 TIE4 (R/W) (0)
3 TIE3 (R/W) (0)
2 TIE2 (R/W) (0)
1 TIE1 (R/W) (0)
0 TIE0 (R/W) (0)
0: Transmission interrupt disabled 1: Transmission interrupt enabled
290
19.6 Classifying the CAN Controller Registers
19.6.14 Reception Complete Register (RCR)
At completion of storing received message in the message buffer (x), RCx becomes 1. If RIEx of the reception complete interrupt enable register (RIER) is 1, an interrupt occurs.
s Reception Complete Register (RCR)
15 Address: 000079H (CAN0) 000089H (CAN1) Read/write: Initial value: RC15 (R/W) (0)
14 RC14 (R/W) (0)
13 RC13 (R/W) (0)
12 RC12 (R/W) (0)
11 RC11 (R/W) (0)
10 RC10 (R/W) (0)
9 RC9 (R/W) (0)
8 RC8 (R/W) (0)
7 Address: 000078H (CAN0) 000088H (CAN1) Read/write: Initial value: RC7 (R/W) (0)
6 RC6 (R/W) (0)
5 RC5 (R/W) (0)
4 RC4 (R/W) (0)
3 RC3 (R/W) (0)
2 RC2 (R/W) (0)
1 RC1 (R/W) (0)
0 RC0 (R/W) (0)
r Conditions for RCx = 0 Write 0 to RCx. After completion of handling received message, write 0 to RCx to set it to 0. Writing 1 to RCx is ignored. 1 is read when a Read Modify Write instruction is perforrmed. Note: If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same time, the bit is set to 1.
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19.6.15 Remote Request Receiving Register (RRTRR)
After a remote frame is stored in the message buffer (x), RRTRx becomes 1 (at the same time as RCx setting to 1).
s Remote Request Receiving Register (RRTRR)
15 Address: 00007BH (CAN0) 00008BH (CAN1) Read/write: Initial value: RRTR15 (R/W) (0)
14 RRTR14 (R/W) (0)
13 RRTR13 (R/W) (0)
12 RRTR12 (R/W) (0)
11 RRTR11 (R/W) (0)
10 RRTR10 (R/W) (0)
9 RRTR9 (R/W) (0)
8 RRTR8 (R/W) (0)
7 Address: 00007AH (CAN0) 00008AH (CAN1) Read/write: Initial value: RRTR7 (R/W) (0)
6 RRTR6 (R/W) (0)
5 RRTR5 (R/W) (0)
4 RRTR4 (R/W) (0)
3 RRTR3 (R/W) (0)
2 RRTR2 (R/W) (0)
1 RRTR1 (R/W) (0)
0 RRTR0 (R/W) (0)
r Conditions for RRTRx = 0 * * * Write 0 to RRTRx. After a received data frame is stored in the message buffer (x) (at the same time as RCx setting to 1). Transmission by the message buffer (x) is completed (TCx of the transmission complete register (TCR) is 1).
Writing 1 to RRTRx is ignored. 1 is read when a Read Modify Write instruction is performed. Note: If setting to 1 by completion of the recieve operation and clearing to 0 by writing occur at the same time, the bit is set to 1.
292
19.6 Classifying the CAN Controller Registers
19.6.16 Receive Overrun Register (ROVRR)
If RCx of the reception complete register (RCR) is 1 when completing storing of a received message in the message buffer (x), ROVRx becomes 1, indicating that reception has overrun.
s Receive Overrun Register (ROVRR)
15 Address: 00007DH (CAN0) 00008DH (CAN1) Read/write: Initial value: ROVR15 (R/W) (0)
14 ROVR14 (R/W) (0)
13 ROVR13 (R/W) (0)
12 ROVR12 (R/W) (0)
11 ROVR11 (R/W) (0)
10 ROVR10 (R/W) (0)
9 ROVR9 (R/W) (0)
8 ROVR8 (R/W) (0)
7 Address: 00007CH (CAN0) 00008CH (CAN1) Read/write: Initial value: ROVR7 (R/W) (0)
6 ROVR6 (R/W) (0)
5 ROVR5 (R/W) (0)
4 ROVR4 (R/W) (0)
3 ROVR3 (R/W) (0)
2 ROVR2 (R/W) (0)
1 ROVR1 (R/W) (0)
0 ROVR0 (R/W) (0)
Writing 0 to ROVRx results in ROVRx = 0. Writing 1 to ROVRx is ignored. After checking that reception has overrun, write 0 to ROVRx to set it to 0. 1 is read when a Read Modify Write instruction is performed. Note: If setting to 1 by completion of the recieve operation and clearing to 0 by writing occur at the same time, the bit is set to 1.
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19.6.17 Reception Interrupt Enable Register (RIER)
Reception interrupt enable register (RIER) enables or disables the reception interrupt by the message buffer (x). The reception interrupt is generated at reception completion (when RCx of the reception completion register (RCR) is 1).
s Reception Interrupt Enable Register (RIER)
15 Address: 00007FH (CAN0) 00008FH (CAN1) Read/write: Initial value: RIE15 (R/W) (0)
14 RIE14 (R/W) (0)
13 RIE13 (R/W) (0)
12 RIE12 (R/W) (0)
11 RIE11 (R/W) (0)
10 RIE10 (R/W) (0)
9 RIE9 (R/W) (0)
8 RIE8 (R/W) (0)
7 Address: 00007EH (CAN0) 00008EH (CAN1) Read/write: Initial value: RIE7 (R/W) (0)
6 RIE6 (R/W) (0)
5 RIE5 (R/W) (0)
4 RIE4 (R/W) (0)
3 RIE3 (R/W) (0)
2 RIE2 (R/W) (0)
1 RIE1 (R/W) (0)
0 RIE0 (R/W) (0)
0: Reception interrupt disabled 1: Reception interrupt enabled
294
19.6 Classifying the CAN Controller Registers
19.6.18 Acceptance Mask Select Register (AMSR)
This register selects masks (acceptance mask) for comparison between the received message ID's and the message buffer ID's.
s Acceptance Mask Select Register (AMSR)
BYTE0
Address: 001C10H (CAN0) 001D10H (CAN1) Read/write: Initial value:
7 AMS3.1 (R/W) (X)
6 AMS3.0 (R/W) (X)
5 AMS2.1 (R/W) (X)
4 AMS2.0 (R/W) (X)
3 AMS1.1 (R/W) (X)
2 AMS1.0 (R/W) (X)
1 AMS0.1 (R/W) (X)
0 AMS0.0 (R/W) (X)
BYTE1
Address: 001C11H (CAN0) 001D11H (CAN1) Read/write: Initial value:
15 AMS7.1 (R/W) (X)
14 AMS7.0 (R/W) (X)
13 AMS6.1 (R/W) (X)
12 AMS6.0 (R/W) (X)
11 AMS5.1 (R/W) (X)
10 AMS5.0 (R/W) (X)
9 AMS4.1 (R/W) (X)
8 AMS4.0 (R/W) (X)
BYTE2
Address: 001C12H (CAN0) 001D12H (CAN1) Read/write: Initial value:
7 AMS11.1 (R/W) (X)
6 AMS11.0 (R/W) (X)
5 AMS10.1 (R/W) (X)
4 AMS10.0 (R/W) (X)
3 AMS9.1 (R/W) (X)
2 AMS9.0 (R/W) (X)
1 AMS8.1 (R/W) (X)
0 AMS8.0 (R/W) (X)
BYTE3
Address: 001C13H (CAN0) 001D13H (CAN1) Read/write: Initial value:
15 AMS15.1 (R/W) (X)
14 AMS15.0 (R/W) (X)
13 AMS14.1 (R/W) (X)
12 AMS14.0 (R/W) (X)
11 AMS13.1 (R/W) (X)
10 AMS13.0 (R/W) (X)
9 AMS12.1 (R/W) (X)
8 AMS12.0 (R/W) (X)
Table 19.6-2 Selection of Acceptance Mask AMSx.1 0 0 1 AMSx.0 0 1 0 Full-bit comparison Full-bit mask Acceptance mask register 0 (AMR0) Acceptance Mask
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CHAPTER 19 CAN CONTROLLER Table 19.6-2 Selection of Acceptance Mask (Continued) AMSx.1 1 Note: AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored AMSx.0 1 Acceptance Mask Acceptance mask register 1 (AMR1)
296
19.6 Classifying the CAN Controller Registers
19.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
There are two acceptance mask registers, AMR0 and AMR1, both of which are available either in the standard frame format or extended frame format. AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format and AM28 to AM0 (29 bits) are used for acceptance masks in the extended format.
s Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
AMR0 BYTE0
Address: 001C14H (CAN0) 001D14H (CAN1) Read/write: Initial value:
7 AM28 (R/W) (X)
6 AM27 (R/W) (X)
5 AM26 (R/W) (X)
4 AM25 (R/W) (X)
3 AM24 (R/W) (X)
2 AM23 (R/W) (X)
1 AM22 (R/W) (X)
0 AM21 (R/W) (X)
AMR0 BYTE1
Address: 001C15H (CAN0) 001D15H (CAN1) Read/write: Initial value:
15 AM20 (R/W) (X)
14 AM19 (R/W) (X)
13 AM18 (R/W) (X)
12 AM17 (R/W) (X)
11 AM16 (R/W) (X)
10 AM15 (R/W) (X)
9 AM14 (R/W) (X)
8 AM13 (R/W) (X)
AMR0 BYTE2
Address: 001C16H (CAN0) 001D16H (CAN1) Read/write: Initial value:
7 AM12 (R/W) (X)
6 AM11 (R/W) (X)
5 AM10 (R/W) (X)
4 AM9 (R/W) (X)
3 AM8 (R/W) (X)
2 AM7 (R/W) (X)
1 AM6 (R/W) (X)
0 AM5 (R/W) (X)
AMR0 BYTE3
Address: 001C17H (CAN0) 001D17H (CAN1) Read/write: Initial value:
15 AM4 (R/W) (X)
14 AM3 (R/W) (X)
13 AM2 (R/W) (X)
12 AM1 (R/W) (X)
11 AM0 (R/W) (X)
10 -- (--) (--)
9 -- (--) (--)
8 -- (--) (--)
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CHAPTER 19 CAN CONTROLLER
AMR1 BYTE0
Address: 001C18H (CAN0) 001D18H (CAN1) Read/write: Initial value:
7 AM28 (R/W) (X)
6 AM27 (R/W) (X)
5 AM26 (R/W) (X)
4 AM25 (R/W) (X)
3 AM24 (R/W) (X)
2 AM23 (R/W) (X)
1 AM22 (R/W) (X)
0 AM21 (R/W) (X)
AMR1 BYTE1
Address: 001C19H (CAN0) 001D19H (CAN1) Read/write: Initial value:
15 AM20 (R/W) (X) 7 AM12 (R/W) (X)
14 AM19 (R/W) (X) 6 AM11 (R/W) (X)
13 AM18 (R/W) (X) 5 AM10 (R/W) (X)
12 AM17 (R/W) (X) 4 AM9 (R/W) (X)
11 AM16 (R/W) (X) 3 AM8 (R/W) (X)
10 AM15 (R/W) (X) 2 AM7 (R/W) (X)
9 AM14 (R/W) (X) 1 AM6 (R/W) (X)
8 AM13 (R/W) (X) 0 AM5 (R/W) (X)
AMR1 BYTE2
Address: 001C1AH (CAN0) 001D1AH (CAN1) Read/write: Initial value:
AMR1 BYTE3
Address: 001C1BH (CAN0) 001D1BH (CAN1) Read/write: Initial value:
15 AM4 (R/W) (X)
14 AM3 (R/W) (X)
13 AM2 (R/W) (X)
12 AM1 (R/W) (X)
11 AM0 (R/W) (X)
10 -- (--) (--)
9 -- (--) (--)
8 -- (--) (--)
r 0: Compare Compare the bit of the acceptance code (ID register IDRx for comparing with the received message ID) corresponding to this bit with the bit of the received message ID. If there is no match, no message is received. r 1: Mask Mask the bit of the acceptance code ID register (IDRx) corresponding to this bit. No comparison is made with the bit of the received message ID. Note: AMR0 and AMR1 should be set when all the message buffers (x) selecting AMR0 and AMR1 are invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffers are valid (BVALx = 1) may cause unnecessary received messages to be stored.
298
19.6 Classifying the CAN Controller Registers
19.6.20 Message Buffers
There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register (IDRx), DLC register (DLCRx), and data register (DTRx).
s Message Buffers
r The message buffer (x) is used both for transmission and reception. r The lower-numbered message buffers are assigned higher priority. * * At transmission, when a request for transmission is made to more than one message buffer, transmission is performed, starting with the lowest-numbered message buffer (See 19.7). At reception, when the received message ID passes through the acceptance filter (mechanism for comparing the acceptance-masked ID of received message and message buffer) of more than one message buffer, the received message is stored in the lowestnumbered message buffer (See 19.8).
r When the same acceptance filter is set in more than one message buffer, the message buffers can be used as a multi-level message buffer. This provides allowance for receiving time (See 19.12). Note: A write operation to message buffers and general-purpose RAM areas should be performed in words to even addresses only. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. When the BVALx bit of the message buffer valid register (BVALR) is 0 (Invalid), the message buffers x (IDRx, DLCRx, and DTRx) can be used as general-purpose RAM. During the receive/transmit operation of the CAN controller, the CAN Controller write/read to/ from the message buffers. If the CPU tries to write/read to/from the message buffers in this period, the CPU has to wait a maximum time of 64 machine cycles. This is also true for the general-purpose RAM.
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CHAPTER 19 CAN CONTROLLER
19.6.21 ID Register x (x = 0 to 15) (IDRx)
IDRegister x (x = 0 to 15) (IDRx) is the ID register for message buffer (x).
s ID Register x (x = 0 to 15) (IDRx)
BYTE0
Address: 001A20H + 4x (CAN0) 001B20H + 4x (CAN1) Read/write: Initial value:
7 ID28 (R/W) (X)
6 ID27 (R/W) (X)
5 ID26 (R/W) (X)
4 ID25 (R/W) (X)
3 ID24 (R/W) (X)
2 ID23 (R/W) (X)
1 ID22 (R/W) (X)
0 ID21 (R/W) (X)
BYTE1
Address: 001A21H + 4x (CAN0) 001B21H + 4x (CAN1) Read/write: Initial value:
15 ID20 (R/W) (X)
14 ID19 (R/W) (X)
13 ID18 (R/W) (X)
12 ID17 (R/W) (X)
11 ID16 (R/W) (X)
10 ID15 (R/W) (X)
9 ID14 (R/W) (X)
8 ID13 (R/W) (X)
BYTE2
Address: 001A22H + 4x (CAN0) 001B22H + 4x (CAN1) Read/write: Initial value:
7 ID12 (R/W) (X)
6 ID11 (R/W) (X)
5 ID10 (R/W) (X)
4 ID9 (R/W) (X)
3 ID8 (R/W) (X)
2 ID7 (R/W) (X)
1 ID6 (R/W) (X)
0 ID5 (R/W) (X)
BYTE3
Address: 001A23H + 4x (CAN0) 001B23H + 4x (CAN1) Read/write: Initial value:
15 ID4 (R/W) (X)
14 ID3 (R/W) (X)
13 ID2 (R/W) (X)
12 ID1 (R/W) (X)
11 ID0 (R/W) (X)
10 -- (--) (--)
9 -- (--) (--)
8 -- (--) (--)
When using the message buffer (x) in the standard frame format (IDEx of the IDE register (IDER) = 0), use 11 bits of ID28 to ID18. When using the buffer in the extended frame format (IDEx = 1), use 29 bits of ID28 to ID0. ID28 to ID0 have the following functions: * * Set acceptance code (ID for comparing with the received message ID). Set transmitted message ID.
Note: In the standard frame format, setting 1s to all bits of ID28 to ID22 is prohibited). * Store the received message ID.
Note: All received message ID bits are stored (even if bits are masked). In the standard frame
300
19.6 Classifying the CAN Controller Registers format, ID17 to ID0 stores image of old message left in the receive shift register. Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. This register should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored.
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CHAPTER 19 CAN CONTROLLER
19.6.22 DLC Register x (x = 0 to 15) (DLCRx)
DLC Register x (x = 0 to 15) (DLCRx) is the DLC register for message buffer x.
s DLC Register x (x = 0 to 15) (DLCRx)
7 Address: 001A60H + 2x (CAN0) 001B60H + 2x (CAN1) Read/write: Initial value: -- (--) (--)
6 -- (--) (--)
5 -- (--) (--)
4 -- (--) (--)
3 DLC3 (R/W) (X)
2 DLC2 (R/W) (X)
1 DLC1 (R/W) (X)
0 DLC0 (R/W) (X)
r Transmission * * Set the data length (byte count) of a transmitted message when a data frame is transmitted (TRTRx of the transmitting RTR register (TRTRR) is 0). Set the data length (byte count) of a requested message when a remote frame is transmitted (TRTRx = 1).
Note: Setting other than 0000 to 1000 (0 to 8 bytes) is prohibited. r Reception * * Store the data length (byte count) of a received message when a data frame is received (RRTRx of the remote frame request receiving register (RRTRR) is 0). Store the data length (byte count) of a requested message when a remote frame is received (RRTRx = 1).
Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored.
302
19.6 Classifying the CAN Controller Registers
19.6.23 Data Register x (x = 0 to 15) (DTRx)
Data register x (x = 0 to 15) (DTRx) is the data register for message buffer (x). This register is used only in transmitting and receiving a data frame but not in transmitting and receiving a remote frame.
s Data Register x (x = 0 to 15) (DTRx)
BYTE0
Address: 001A80H + 8x (CAN0) 001B80H + 8x (CAN1) Read/write: Initial value:
7 D7 (R/W) (X)
6 D6 (R/W) (X)
5 D5 (R/W) (X)
4 D4 (R/W) (X)
3 D3 (R/W) (X)
2 D2 (R/W) (X)
1 D1 (R/W) (X)
0 D0 (R/W) (X)
BYTE1
Address: 001A81H + 8x (CAN0) 001B81H + 8x (CAN1) Read/write: Initial value:
15 D7 (R/W) (X)
14 D6 (R/W) (X)
13 D5 (R/W) (X)
12 D4 (R/W) (X)
11 D3 (R/W) (X)
10 D2 (R/W) (X)
9 D1 (R/W) (X)
8 D0 (R/W) (X)
BYTE2
Address: 001A82H + 8x (CAN0) 001B82H + 8x (CAN1) Read/write: Initial value:
7 D7 (R/W) (X)
6 D6 (R/W) (X)
5 D5 (R/W) (X)
4 D4 (R/W) (X)
3 D3 (R/W) (X)
2 D2 (R/W) (X)
1 D1 (R/W) (X)
0 D0 (R/W) (X)
BYTE3
Address: 001A83H + 8x (CAN0) 001B83H + 8x (CAN1) Read/write: Initial value:
15 D7 (R/W) (X)
14 D6 (R/W) (X)
13 D5 (R/W) (X)
12 D4 (R/W) (X)
11 D3 (R/W) (X)
10 D2 (R/W) (X)
9 D1 (R/W) (X)
8 D0 (R/W) (X)
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CHAPTER 19 CAN CONTROLLER
BYTE4
Address: 001A84H + 8x (CAN0) 001B84H + 8x (CAN1) Read/write: Initial value:
7 D7 (R/W) (X)
6 D6 (R/W) (X)
5 D5 (R/W) (X)
4 D4 (R/W) (X)
3 D3 (R/W) (X)
2 D2 (R/W) (X)
1 D1 (R/W) (X)
0 D0 (R/W) (X)
BYTE5
Address: 001A85H + 8x (CAN0) 001B85H + 8x (CAN1) Read/write: Initial value:
15 D7 (R/W) (X)
14 D6 (R/W) (X)
13 D5 (R/W) (X)
12 D4 (R/W) (X)
11 D3 (R/W) (X)
10 D2 (R/W) (X)
9 D1 (R/W) (X)
8 D0 (R/W) (X)
BYTE6
Address: 001A86H + 8x (CAN0) 001B86H + 8x (CAN1) Read/write: Initial value:
7 D7 (R/W) (X)
6 D6 (R/W) (X)
5 D5 (R/W) (X)
4 D4 (R/W) (X)
3 D3 (R/W) (X)
2 D2 (R/W) (X)
1 D1 (R/W) (X)
0 D0 (R/W) (X)
BYTE7
Address: 001A87H + 8x (CAN0) 001B87H + 8x (CAN1) Read/write: Initial value:
15 D7 (R/W) (X)
14 D6 (R/W) (X)
13 D5 (R/W) (X)
12 D4 (R/W) (X)
11 D3 (R/W) (X)
10 D2 (R/W) (X)
9 D1 (R/W) (X)
8 D0 (R/W) (X)
r Sets transmitted message data (any of 0 to 8 bytes). Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. r Stores received message data. Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. Even if the received message data is less than 8 bytes, the remaining bytes of the data register (DTRx), to which data are stored, are undefined. Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored.
304
19.7 Transmission of CAN Controller
19.7 Transmission of CAN Controller
When 1 is written to TREQx of the transmission request register (TREQR), transmission by the message buffer (x) starts. At this time, TREQx becomes 1 and TCx of the transmission complete register (TCR) becomes 0.
s Starting Transmission of the CAN Controller If RFWTx of the remote frame receiving wait register (RFWTR) is 0, transmission starts immediately. If RFWTx is 1, transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR) becomes 1). If a request for transmission is made to more than one message buffer (more than one TREQx is 1), transmission is performed, starting with the lowest-numbered message buffer. Message transmission to the CAN bus (by the transmit output pin TX) starts when the bus is idle. If TRTRx of the transmission RTR register (TRTRR) is 0, a data frame is transmitted. If TRTRx is 1, a remote frame is transmitted. If the message buffer competes with other CAN controllers on the CAN bus for transmission and arbitration fails, or if an error occurs during transmission, the message buffer waits until the bus is idle and repeats retransmission until it is successful. s Canceling a Transmission Request from the CAN Controller
r Canceling by transmission cancel register (TCANR) A transmission request for message buffer (x) having not executed transmission during transmission pending can be canceled by writing 1 to TCANx of the transmission cancel register (TCANR). At completion of cancellation, TREQx becomes 0. r Canceling by storing received message The message buffer (x) having not executed transmission despite transmission request also performs reception. If the message buffer (x) has not executed transmission despite a request for transmission of a data frame (TRTRx = 0 or TREQx = 1), the transmission request is canceled after storing received data frames passing through the acceptance filter (TREQx = 0). Note: A transmission request is not canceled by storing remote frames (TREQx = 1 remains unchanged). If the message buffer (x) has not executed transmission despite a request for transmission of a remote frame (TRTRx = 1 or TREQx = 1), the transmission request is canceled after storing received remote frames passing through the acceptance filter (TREQx = 0). Note: The transmission request is canceled by storing either data frames or remote frames.
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CHAPTER 19 CAN CONTROLLER s Completing Transmission of the CAN Controller When transmission is successful, RRTRx becomes 0, TREQx becomes 0, and TCx of the transmission complete register (TCR) becomes 1. If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable register (TIER) is 1), an interrupt occurs. s Transmission Flowchart of the CAN Controller Figure 19.7-1 shows a transmission flowchart of the CAN controller. Figure 19.7-1 Transmission Flowchart of the CAN Controller
Transmission request (TREQx := 1)
TCx := 0
0 TREQx? 1 0 RFWTx? 1 0 RRTRx? 1 If there are any other message buffers meeting the above conditions, select the lowest-numbered message buffer.
Is the bus idle? YES 0 TRTRx? A data frame is transmitted.
NO
1
A remote frame is transmitted.
Is transmission successful? YES RRTRx := 0 TREQx := 0 TCx := 1
NO 0 TCANx? 1 TREQx := 0 1
TIEx? 0 A transmission complete interrupt occurs.
End of transmission
306
19.8 Reception of CAN Controller
19.8 Reception of CAN Controller
Reception starts when the start of data frame or remote frame (SOF) is detected on the CAN bus.
s Acceptance Filtering The received message in the standard frame format is compared with the message buffer (x) set in the standard frame format (IDEx of the IDE register (IDER) is 0). The received message in the extended frame format is compared with the message buffer (x) set (IDEx is 1) in the extended frame format. If all the bits set to Compare by the acceptance mask agree after comparison between the received message ID and acceptance code (ID register (IDRx) for comparing with the received message ID), the received message passes to the acceptance filter of the message buffer (x). s Storing Received Message When the receive operation is successful, received messages are stored in a message buffer x including IDs passed through the acceptance filter. When receiving data frames, received messages are stored in the ID register (IDRx), DLC register (DLCRx), and data register (DTRx). Even if received message data is less than 8 bytes, some data is stored in the remaining bytes of the DTRx and its value is undefined. When receiving remote frames, received messages are stored only in the IDRx and DLCRx, and the DTRx remains unchanged. If there is more than one message buffer including IDs passed through the acceptance filter, the message buffer x in which received messages are to be stored is determined according to the following rules. * The order of priority of the message buffer x (x = 0 to 15) rises as its number lower; in other words, message buffer 0 is given the highest and the message buffer 15 is given the lowest priority. Basically, message buffers with the RCx bit of 0 in the receive completion register (RCR) are preferred in storing received messages. If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare (for message buffers with the AMSx.1 and AMSx.0 bits set to 00), received messages are stored irrespective of the value of the RCx bit of the RCR. If there are message buffers with the RCx bit of the RCR set to 0, or with the bits of the AMSR set to All Bits Compare, received messages are stored in the lowest-number (highestpriority) message buffer x. If there are no message buffers above-mentioned, received messages are stored in a lowernumber message buffer x. Message buffers should be arranged in ascending numeric order. The lowest message buffers should be with All Bits Compare, then AMR0 or AMR1 masks. And The highest message buffers should be with All Bits Mask.
* *
*
* *
Figure 19.8-1 shows a flowchart for determining the message buffer (x) where received messages are to be stored. It is recommended that message buffers be arranged in the
307
CHAPTER 19 CAN CONTROLLER following order: message buffers in which each AMSR bit is set to All Bits Compare, message buffers using AMR0 or AMR1, and message buffers in which each AMSR bit is set to All Bits Mask. Figure 19.8-1 Flowchart Determining Message Buffer (x) where Received Messages Stored
Start
Are message buffers with RCx set to 0 or with AMSx.1 and AMSx.0 set to 00 found? YES Select the lowest-numbered message buffer.
NO
Select the lowest-numbered message buffer.
End
s Receive Overrun When a message is stored in the message buffer with the corresponding RCx being already set to 1, it will results in receive overrun. In this case, the corresponding ROVRx bit in the receive overrun register ROVRR is set to 1. s Processing for Reception of Data Frame and Remote Frame
r Processing for reception of data frame RRTRx of the remote request receiving register (RRTRR) becomes 0. TREQx of the transmission request register (TREQR) becomes 0 (immediately before storing the received message). A transmission request for message buffer (x) having not executed transmission will be canceled. Note: A request for transmission of either a data frame or remote frame is canceled. r Processing for reception of remote frame RRTRx becomes 1. If TRTRx of the transmitting RTR register (TRTRR) is 1, TREQx becomes 0. As a result, the request for transmitting remote frame to message buffer having not executed transmission will be canceled. Note: A request for data frame transmission is not canceled. For cancellation of a transmission request, see Figure 19.7. s Completing Reception RCx of the reception complete register (RCR) becomes 1 after storing the received message. If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is 1), an 308
19.8 Reception of CAN Controller interrupt occurs. Note: This CAN controller will not receive any messages transmitted by itself.
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CHAPTER 19 CAN CONTROLLER
19.9 Reception Flowchart of CAN Controller
Figure 19.9-1 shows a reception flowchart of the CAN controller.
s Reception Flowchart of the CAN Controller
Figure 19.9-1 Reception Flowchart of the CAN Controller
Detection of start of data frame or remote frame (SOF)
Is any message buffer (x) passing to the acceptance filter found? YES Is reception successful? YES Determine message buffer (x) where received messages to be stored. NO
NO
Store the received message in the message buffer (x).
1 RCx? 0 ROVRx := 1
Data frame
Received message?
Remote frame
RRTRx := 0 1
RRTRx := 1
TRTRx? TREQx := 0 0
RCx := 1 1 RIEx? 0 A reception interrupt occurs.
End of reception
310
19.10 How to Use the CAN Controller
19.10 How to Use the CAN Controller
The following settings are required to use the CAN controller: * Bit timing * Frame format * ID * Acceptance filter * Low-power consumption mode
s Setting Bit Timing The bit timing register (BTR) should be set during bus operation stop (when the bus operation stop bit (HALT) of the control status register (CSR) is 1). After the setting completion, write 0 to HALT to cancel bus operation stop. s Setting Frame Format Set the frame format used by the message buffer (x). When using the standard frame format, set IDEx of the IDE register (IDER) to 0. When using the extended frame format, set IDEx to 1. This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. s Setting ID Set the message buffer (x) ID to ID28 to ID0 of ID register (IDRx). The message buffer (x) ID need not be set to ID11 to ID0 in the standard frame format. The message buffer (x) ID is used as a transmission message at transmission and is used as an acceptance code at reception. This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. s Setting Acceptance Filter The acceptance filter of the message buffer (x) is set by an acceptance code and acceptance mask set. It should be set when the acceptance message buffer (x) is invalid (BVALx of the message buffer enable register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. Set the acceptance mask used in each message buffer (x) by the acceptance mask select register (AMSR). The acceptance mask registers (AMR0 and AMR1) should also be set if used (For the setting details, see 19.6.18 and 19.6.19). The acceptance mask should be set so that a transmission request may not be canceled when unnecessary received messages are stored. For example, it should be set to a full-bit comparison if only one specific ID is used for the transmission. s Setting Low-power Consumption Mode To set the F2MC-16LX in a low-power consumption mode (Stop, Watch, Hardware Standby,
311
CHAPTER 19 CAN CONTROLLER etc.), write 1 to the bus operation stop bit (HALT) of the control status register (CSR), and then check that the bus operation has stopped (HALT = 1).
312
19.11 Procedure for Transmission by Message Buffer (x)
19.11 Procedure for Transmission by Message Buffer (x)
After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to 1 to activate the message buffer (x).
s Procedure for Transmission by Message Buffer (x)
r Setting transmit data length code Set the transmit data length code (byte count) to DLC3 to DLC0 of the DLC register (DLCRx). For data frame transmission (when TRTRx of the transmission RTR register (TRTRR) is 0), set the data length of the transmitted message. For remote frame transmission (when TRTRx = 1), set the data length (byte count) of the requested message. Note: Setting other than 0000 to 1000 (0 to 8 bytes) is prohibited. r Setting transmit data (only for transmission of data frame) For data frame transmission (when TRTRx of the transmission register (TRTRR) is 0), set data as the count of byte transmitted in the data register (DTRx). Note: Transmit data should be rewritten while the TREQx bit of the transmission request register (TREQR) set to 0. There is no need for setting the BVALx bit of the message buffer valid register (BVALR) to 0. Setting the BVALx bit to 0 may cause incoming remote frame to be lost. r Setting transmission RTR register For data frame transmission, set TRTRx of the transmission RTR register (TRTRR) to 0. For remote frame transmission, set TRTRx to 1. r Setting conditions for starting transmission (only for transmission of data frame) Set RFWTx of the remote frame receiving wait register (RFWTR) to 0 to start transmission immediately after a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is 1 and TRTRx of the transmission RTR register (TRTRR) is 0). Set RFWTx to 1 to start transmission after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR) becomes 1) after a request for data frame transmission is set (TREQx = 1 and TRTRx = 0). Note: Remote frame transmission can not be made, if RFWTx is set to 1. r Setting transmission complete interrupt When generating a transmission complete interrupt, set TIEx of the transmission complete interrupt enable register (TIER) to 1.
313
CHAPTER 19 CAN CONTROLLER When not generating a transmission complete interrupt, set TIEx to 0. r Setting transmission request For a transmission request, set TREQx of the transmission request register (TREQR) to 1. r Canceling transmission request When canceling a pending request for transmission to the message buffer (x), write 1 to TCANx of the transmission cancel register (TCANR). Check TREQx. For TREQx = 0, transmission cancellation is terminated or transmission is completed. Check TCx of the transmission complete register (TCR). For TCx = 0, transmission cancellation is terminated. For TCx = 1, transmission is completed. r Processing for completion of transmission If transmission is successful, TCx of the transmission complete register (TCR) becomes 1. If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable register (TIER) is 1), an interrupt occurs. After checking the transmission completion, write 0 to TCx to set it to 0. This cancels the transmission complete interrupt. In the following cases, the pending transmission request is canceled by receiving and storing a message. * * * Request for data frame transmission by reception of data frame Request for remote frame transmission by reception of data frame Request for remote frame transmission by reception of remote frame
Request for data frame transmission is not canceled by receiving and storing a remote frame. ID and DLC, however, are changed by the ID and DLC of the received remote frame. Note that the ID and DLC of data frame to be transmitted become the value of received remote frame.
314
19.12 Procedure for Reception by Message Buffer (x)
19.12 Procedure for Reception by Message Buffer (x)
After setting the bit timing, frame format, ID, and acceptance filter, make the settings described below.
s Procedure for Reception by Message Buffer (x)
r Setting reception interrupt To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to 1. To disable reception interrupt, set RIEx to 0. r Starting reception When starting reception after setting, set BVALx of the message buffer valid register (BVALR) to 1 to make the message buffer (x) valid. r Processing for reception completion If reception is successful after passing to the acceptance filter, the received message is stored in the message buffer (x) and RCx of the reception complete register (RCR) becomes 1. For data frame reception, RRTRx of the remote request receiving register (RRTRR) becomes 0. For remote frame reception, RRTRx becomes 1. If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is 1), an interrupt occurs. After checking the reception completion (RCx = 1), process the received message. After completion of processing the received message, check ROVRx of the reception overrun register (ROVRR). If ROVRx = 0, the processed received message is valid. Write 0 to RCRx to set it to 0 (the reception complete interrupt is also canceled) to terminate reception. If ROVRx = 1, a reception overrun occurred and the next message may have overwritten the processed message. In this case, received messages should be processed again after setting the ROVRx bit to 0 by writing 0 to it. Figure 19.12-1 shows an example of receive interrupt handling.
315
CHAPTER 19 CAN CONTROLLER Figure 19.12-1 Example of Receive Interrupt Handling
Interrupt with RCx = 1
Read received messages.
A := ROVRx ROVRx := 0
A = 0? YES RCx := 0
NO
End
316
19.13 Setting Configuration of Multi-level Message Buffer
19.13 Setting Configuration of Multi-level Message Buffer
If the receptions are performed frequently, or if several different ID's of messages are received, in other words, if there is insufficient time for handling messages, more than one message buffer can be combined into a multi-level message buffer to provide allowance for processing time of the received message by CPU.
s Setting Configuration of Multi-level Message Buffer To provide a multi-level message buffer, the same acceptance filter must be set in the combined message buffers. If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare ((AMSx.1, AMSx.0) = (0, 0)), multi-level message configuration of message buffers is not allowed. This is because All Bits Compare causes received messages to be stored irrespective of the value of the RCx bit of the receive completion register (RCR), so received messages are always stored in lower-numbered (lower-priority) message buffers even if All Bits Compare and identical acceptance code (ID register (IDRx)) are specified for more than one message buffer. Therefore, All Bits Compare and identical acceptance code should not be specified for more than one message buffer. Figure 19.13-1 shows operational examples of multi-level message buffers.
317
CHAPTER 19 CAN CONTROLLER Figure 19.13-1 Examples of Operation of Multi-level Message Buffer
Initialization AMSR 10 10 10 AMS15, AMS14, AMS13 ...
Select AMR0.
AM28 to AM18 AMS0 0000 1111 111 ... 0101 0000 000 0101 0000 000 0101 0000 000 0 0 0 IDE ... ... ... Mask RCR 0 ROVRR 0 0 0 0 0 RC15, RC14, RC13 ... ... ROVR15, ROVR14, ROVR13
ID28 to ID18 Message buffer 13 Message buffer 14 Message buffer 15
Message receiving ID28 to ID18 Message receiving
"The received message is stored in message buffer 13. IDE 0101 1111 000 0 ...
Message buffer 13 Message buffer 14 Message buffer 15 Message receiving Message receiving
0101 1111 000 0101 0000 000 0101 0000 000
0 0 0
... ... ...
RCR 0 ROVRR 0
0 0
1 0
... ...
"The received message is stored in message buffer 14. 0101 1111 001 0 ...
Message buffer 13 Message buffer 14 Message buffer 15 Message receiving Message receiving
0101 1111 000 0101 1111 001 0101 0000 000
0 0 0
... ... ...
RCR 0 ROVRR 0
1 0
1 0
... ...
"The received message is stored in message buffer 15. 0101 1111 010 0 ...
Message buffer 13 Message buffer 14 Message buffer 15
0101 1111 000 0101 1111 001 0101 1111 010
0 0 0
... ... ...
RCR 1 ROVRR 0
1 0
1 0
... ...
Message receiving "An overrun occurs (ROVR13 = 1) and the received message is stored in message buffer 13. Message receiving 0101 1111 011 0 ...
Message buffer 13 Message buffer 14 Message buffer 15
0101 1111 011 0101 1111 001 0101 1111 010
0 0 0
... ... ...
RCR 1 ROVRR 0
1 0
1 1
... ...
Note: Four messages are received with the same acceptance filter set in message buffers 13, 14 and 15.
318
CHAPTER 20
STEPPING MOTOR CONTROLLER
This chapter explains the functions and operations of the stepping motor controller. 20.1 Outline of Stepping Motor Controller 20.2 Stepping Motor Controller Registers 20.3 PWM 1&2 Select
319
CHAPTER 20 STEPPING MOTOR CONTROLLER
20.1 Outline of Stepping Motor Controller
The Stepping Motor Controller consists of two PWM Pulse Generators, four motor drivers, drivers and Selector Logic. The four motor drivers have high output drive capabilities and they can be directly connected to the four ends of two motor coils. The combination of the PWM Pulse Generators and Selector Logic is designed to control the rotation of the motor. A synchronization mechanism assures the synchronous operations of the two PWMs. The following sections describe the Stepping Motor Controller 0 only. The other controllers have the same function. The register addresses are found in the I/O map.
s Block Diagram of Stepping Motor Controller Figure 20.1-1 shows a block diagram of the stepping motor controller. Figure 20.1-1 Block Diagram of Stepping Motor Controllerr
Machine Clock OE1 CK Prescaler PWM1 pulse generator EN P1 P0 PWM Selector Output enable PWM1P0
PWM1M0
PWM1 Compare register
PWM1 Select register
OE2 CK PWM2 pulse generator CE EN PWM Load PWM2 Compare register BS PWM2 Select register Selector
Output enable PWM2P0
PWM2M0
320
20.2 Stepping Motor Controller Registers
20.2 Stepping Motor Controller Registers
The stepping motor controller has the following five types of registers: * PWM control 0 register (PWMC0) * PWM1 compare 0 register (PWC10) * PWM2 compare 0 register (PWC20) * PWM1 select register (PWS10) * PWM2 select register (PWS20)
s Stepping Motor Controller Registers
PWM Control 0 register Address: 000062H
7 OE2
6 OE1 (R/W) (0)
5 P1 (R/W) (0)
4 P0 (R/W) (0)
3 CE (R/W) (0)
2
1
0 TST (R/W) (0)
Bit number PWC0
Read/write Initial value PWM1 Compare 0 register Address: 001950H
(R/W) (0)
7 D7
6 D6 (R/W) (X) 14 D6 (R/W) (X)
5 D5 (R/W) (X) 13 D5 (R/W) (X)
4 D4 (R/W) (X) 12 D4 (R/W) (X)
3 D3 (R/W) (X) 11 D3 (R/W) (X)
2 D2 (R/W) (X) 10 D2 (R/W) (X) 9 D1 (R/W) (X)
1 D1 (R/W) (X) 8 D0 (R/W) (X)
0 D0 (R/W) (X)
Bit number PWC10
Read/write Initial value PWM2 Compare 0 register Address: 001951H 15
(R/W) (X)
Bit number PWC20
D7 Read/write Initial value PWM1 Select register Address: 001952H 7 (R/W) (X)
6
5 P2
4 P1 (R/W) (0) 12 P1 (R/W) (0) 11 P0 (R/W) (0)
3 P0 (R/W) (0)
2 M2 (R/W) (0) 10 M2 (R/W) (0) 9 M1 (R/W) (0)
1 M1 (R/W) (0) 8 M0 (R/W) (0)
0 M0 (R/W) (0)
Bit number PWS10
Read/write Initial value PWM2 Select register Address: 001953H BS Read/write Initial value (R/W) (0) P2 15 14
(R/W) (0) 13
Bit number PWS20
(R/W) (0)
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CHAPTER 20 STEPPING MOTOR CONTROLLER
20.2.1 PWM Control 0 register
The PWM control 0 register starts and stops the stepping motor controller, controls interrupts, and sets the external output pins.
s PWM Control 0 Register
PWM Control 0 register Address: 000062H
7 OE2
6 OE1 (R/W) (0)
5 P1 (R/W) (0)
4 P0 (R/W) (0)
3 CE (R/W) (0)
2
1
0 TST (R/W) (0)
Bit number PWC0
Read/write Initial value
(R/W) (0)
[bits 7] OE2 : Output enable bit When this bit is set to "1", the external pins are assigned as PWM2P0 and PWM2M0 outputs. Otherwise they can be used as general purpose IO. [bits 6] OE1 : Output enable bit When this bit is set to "1", the external pins are assigned as PWM1P0 and PWM1M0 outputs. Otherwise they can be used as general purpose IO. [bits 5 to 4] P1 to P0 : Operation clock select bits These bits specify the clock input signal for the PWM pulse generators. P1 0 0 1 1 P0 0 1 0 1 Clock input Machine clock 1/2 Machine clock 1/4 Machine clock 1/8 Machine clock
[bits 3] CE : Count enable bit This bit enables the operation of the PWM pulse generators. When it is set to "1", the PWM pulse generators start their operation. Note that the PWM2 pulse generator starts the operation one machine clock cycle after the PWM1 pulse generators is started. This is to help reduce the switching noise from the output drivers. [bits 0] TST : Test bit This bit is for the device test. In user applications, it should always be set to "0".
322
20.2 Stepping Motor Controller Registers
20.2.2 PWM1&2 Compare Registers
The contents of the two 8-bit compare registers determine the widths of PWM pulses. The stored value of "00H" represents the PWM duty of 0% and "FFH" represents the duty of 99.6%.
s PWM1&2 Compare Registers PWM1&2 compare registers are accessible at any time, however the modified values are reflected to the pulse width at the end of the current PWM cycle after the BS bit of the PWM2 Select register is set to "1".
PWM1 Compare 0 register Address: 001950H 7 D7 Read/write Initial value PWM2 Compare 0 register Address: 001951H D7 Read/write Initial value (R/W) (X) D6 (R/W) (X) D5 (R/W) (X) D4 (R/W) (X) D3 (R/W) (X) D2 (R/W) (X) D1 (R/W) (X) D0 (R/W) (X) 15 (R/W) (X) 14 6 D6 (R/W) (X) 5 D5 (R/W) (X) 13 4 D4 (R/W) (X) 12 3 D3 (R/W) (X) 11 2 D2 (R/W) (X) 10 9 1 D1 (R/W) (X) 8 0 D0 (R/W) (X) Bit number PWC20 Bit number PWC10
One PWM Cycle 256 input clock cycles Register value 00h
80h 128 input clock cycles FFh 255 input clock cycles
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CHAPTER 20 STEPPING MOTOR CONTROLLER
20.3 PWM1&2 Select Registers
The PWM1 and PWM2 select registers select 0, 1, the PWM pulse, or high impedance for the external pin output of the stepping motor controller.
s PWM1&2 Select Registers
PWM1 Select register Address: 001952H 7 6 5 P2 Read/write Initial value PWM2 Select register Address: 001953H BS Read/write Initial value (R/W) (0) P2 (R/W) (0) P1 (R/W) (0) P0 (R/W) (0) M2 (R/W) (0) M1 (R/W) (0) M0 (R/W) (0) 15 14 (R/W) (0) 13 4 P1 (R/W) (0) 12 11 3 P0 (R/W) (0) 2 M2 (R/W) (0) 10 9 1 M1 (R/W) (0) 8 0 M0 (R/W) (0) Bit number PWS20 Bit number PWS10
[bits 14] BS : Update bit This bit is prepared to synchronize the settings for the PWM outputs. Any modifications in the two compare registers and two select registers are not reflected to the output signals until this bit is set. When this bit is set to "1", the PWM pulse generators and selectors load the register contents at the end of the current PWM cycle. The BS bit is reset to "0" automatically at the beginning of the next PWM cycle. If the BS bit is set to "1" by software at the same time as this automatic reset, the BS bit is set to "1" (or remains unchanged) and the automatic reset is cancelled. [bits 13 to 11] P2 to P0 : Output Select bits These bits selects the output signal at PWM2P0. [bits 10 to 8] M2 to M0 : Output Select bits These bits selects the output signal at PWM2M0. [bits 5 to 3] P2 to P0 : Output Select bits These bits selects the output signal at PWM1P0. [bits 2 to 0] M2 to M0 : Output Select bits These bits selects the output signal at PWM1M0. The following table shows the relationship between the output levels and select bits. P2 0 0 P1 0 0 P0 0 1 PWMnP0 L H M2 0 0 M1 0 0 M0 0 1 PWMnM0 L H
324
20.3 PWM1&2 Select Registers
P2 0 1
P1 1 X
P0 X X
PWMnP0 PWM pulses High impedance
M2 0 1
M1 1 X
M0 X X
PWMnM0 PWM pulses High impedance
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CHAPTER 20 STEPPING MOTOR CONTROLLER
326
CHAPTER 21
SOUND GENERATOR
This chapter explains the functions and operations of the sound generator. 21.1 Outline of Sound Generator 21.2 Sound Generator Registers
327
CHAPTER 21 SOUND GENERATOR
21.1 Outline of Sound Generator
The Sound Generator consists of the Sound Control register, Frequency Data register, Amplitude Data register, Decrement Grade register, Tone Count register, PWM pulse generator, Frequency counter, Decrement counter and Tone Pulse counter.
s Block Diagram of Sound Generator Figure 21.1-1 shows a block diagram of the sound generator. Figure 21.1-1 Block Diagram of Sound Generator
Clock input
Prescaler
8bit PWM pulse Generator CO EN PWM reload Amplitude Data register DEC Decrement Counter CI
Frequency Counter CO EN reload
Toggle Flip-flop D EN 1/d Q
S1
S0
Decrement Grade register DEC
CI CO EN OE1
SGA OE1
Decrement Grade register
Mix SGO
Tone Pulse Counter
TONE OE2 CI CO EN
OE2
Tone Count register
INTE
INT
ST IRQ
328
21.2 Sound Generator Registers
21.2 Sound Generator Registers
The sound generator has the following types of registers: * Sound control register (SGCR) * Frequency data register (SGFR) * Amplitude data register (SGAR) * Decrement grade register (SGDR) * Tone count register (SGTR)
s Sound Generator Registers
Sound Control register Address: 00005EH
7 S1
6 S0 (R/W) (0) 13
5 TONE (R/W) (0) 12
4 OE2
3 OE1
2 INTE (R/W) (0)
1 INT (R/W) (0) 9 BUSY (R) (0) 8 DEC (R/W) (0)
0 ST (R/W) (0)
Bit number SGCR
Read/write Initial value 15 Address: 00005FH TST Read/write Initial value Frequecny Data register Address: 001946H
(R/W) (0) 14
11
10
Bit number SGCR
(R/W) (0)
7 D7
6 D6 (R/W) (X) 14 D6 (R/W) (0)
5 D5 (R/W) (X) 13 D5 (R/W) (0)
4 D4 (R/W) (X) 12 D4 (R/W) (0)
3 D3 (R/W) (X) 11 D3 (R/W) (0)
2 D2 (R/W) (X) 10 D2 (R/W) (0) 9 D1 (R/W) (0)
1 D1 (R/W) (X) 8 D0 (R/W) (0)
0 D0 (R/W) (X)
Bit number SGFR
Read/write Initial value Amplitude Data register Address: 001947H 15
(R/W) (X)
Bit number SGAR
D7 Read/write Initial value Decrement Grade register Address: 001948H 7 D7 Read/write Initial value Tone Count register Address: 001949H D7 Read/write Initial value (R/W) (X) 15 (R/W) (X) (R/W) (0)
6 D6 (R/W) (X) 14 D6 (R/W) (X)
5 D5 (R/W) (X) 13 D5 (R/W) (X)
4 D4 (R/W) (X) 12 D4 (R/W) (X) 11 D3 (R/W) (X)
3 D3 (R/W) (X)
2 D2 (R/W) (X) 10 D2 (R/W) (X) 9 D1 (R/W) (X)
1 D1 (R/W) (X) 8 D0 (R/W) (X)
0 D0 (R/W) (X)
Bit number SGDR
Bit number SGTR
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CHAPTER 21 SOUND GENERATOR
21.2.1 Sound Control Register
The sound control register controls the operation status of the sound generator by controlling interrupts and setting the external output pins.
s Sound Control Register
Sound Control register Address: 00005EH
7 S1
6 S0 (R/W) (0) 13
5 TONE (R/W) (0) 12
4 OE2
3 OE1
2 INTE (R/W) (0)
1 INT (R/W) (0) 9 BUSY (R) (0) 8 DEC (R/W) (0)
0 ST (R/W) (0)
Bit number SGCR
Read/write Initial value 15 Address: 00005FH TST Read/write Initial value
(R/W) (0) 14
11
10
Bit number SGCR
(R/W) (0)
[bits 15] TST : Test bit This bit is prepared for the device test. In any user applications, it should be set to "0". [bits 9] BUSY : Busy bit This bit indicates whether the Sound Generator is in operation. This bit is set to "1" upon the ST bit is set to "1". It is reset to "0" when the ST bit is reset to "0" and the operation is completed at the end of one tone cycle. Any write instructions performed on this bit has no effect. [bits 8] DEC : Auto-decrement enable bit The DEC bit is prepared for an automatic de-gradation of the sound in conjunction with the Decrement Grade register. If this bit is set to "1", the stored value in the Amplitude Data register is decremented by 1(one), every time when the Decrement counter counts the number of tone pulses from the toggle flip-flop specified by the Decrement Grade register. [bits 7 to 6] S1 to S0 : Operation clock select bits These bits specify the clock input signal for the Sound Generator. S1 0 0 1 1 S0 0 1 0 1 Clock input Machine clock 1/2 Machine clock 1/4 Machine clock 1/8 Machine clock
330
21.2 Sound Generator Registers [bits 5] TONE : Tone output bit When this bit is set to "1", the SGO signal becomes a simple square-waveform (tone pulses) from the toggle flip-flop. Otherwise it is the mixed (AND logic) signal of the tone and PWM pulses. [bits 4] OE2 : Sound output enable bit When this bit is set to "1", the external pin is assigned as the SGO output. Otherwise the pin can be used as a general purpose IO. To enable the SGO output, the corresponding bit of the Port Direction register should also be set to "1". [bits 3] OE1 : Amplitude output enable bit When this bit is set to "1", the external pin is assigned as the SGA output. Otherwise the pin can be used as a general purpose IO. To enable the SGA output, the corresponding bit of the Port Direction register should also be set to "1". The SGA signal is the PWM pulses from the PWM pulse generator representing the amplitude of the sound. [bits 2] INTE : Interrupt enable bit This bit enables the interrupt signal of the Sound Generator. When this bit is "1" and the INT bit is set to "1", the Sound Generator signals an interrupt. [bits 1] INT : Interrupt bit This bit is set to "1" when the Tone Pulse counter counts the number of the tone pulses specified by the Tone Count register and Decrement Grade register. This bit is reset to "0" by writing "0". Writing "1" has no effect and Read-Modify-Write instructions always result in reading "1". [bits 0] ST : Start bit This bit is for starting the operation of the Sound Generator. While this bit is "1", the Sound Generator perform its operation. When this bit is reset to "0", the Sound Generator stops its operation at the end of the current tone cycle. The BUSY bit indicates whether the Sound Generator is fully stopped.
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CHAPTER 21 SOUND GENERATOR
21.2.2 Frequency Data register
The Frequency Data register stores the reload value for the Frequency counter. The stored value represents the frequency of the sound (or the tone signal from the toggle flip-flop). The register value is reloaded into the counter at every transition of the toggle signal. The following figure shows the relationship between the tone signal and the register value.
s Frequency Data Register
Frequency Data register Address: 001946H 7 D7 Read/write Initial value (R/W) (X) 6 D6 (R/W) (X) 5 D5 (R/W) (X) 4 D4 (R/W) (X) 3 D3 (R/W) (X) 2 D2 (R/W) (X) 1 D1 (R/W) (X) 0 D0 (R/W) (X) Bit number SGFR
Figure 21.2-1 shows the relationship between a tone signal and a register value. Figure 21.2-1 Relationship between Tone Signal and Register Value
One Tone Cycle
Tone signal (register value+1) x One PWM cycle (register value+1) x One PWM cycle
It should be noted that modifications of the register value while operation may alter the duty cycle of 50% depending on the timing of the modification.
332
21.2 Sound Generator Registers
21.2.3 Amplitude Data Register
The Amplitude Data register stores the reload value for the PWM pulse generator. The register value represents the amplitude of the sound. The register value is reloaded into the PWM pulse generator at the end of every tone cycle.
s Amplitude Data Register
Amplitude Data register Address: 001947H
15 D7
14 D6 (R/W) (0)
13 D5 (R/W) (0)
12 D4 (R/W) (0)
11 D3 (R/W) (0)
10 D2 (R/W) (0)
9 D1 (R/W) (0)
8 D0 (R/W) (0)
Bit number SGAR
Read/write Initial value
(R/W) (0)
When the DEC bit is "1" and the Decrement counter reaches its reload value, this register value is decremented by 1(one). And when the register value reaches "00", further decrements are not performed. However the sound generator continues its operation until the ST bit is cleared. Figure 12.2-2 shows the relationship between the register value and the PWM pulse. Figure 21.2-2 Relationship between Register Value and PWM Pulse
One PWM Cycle 256 input clock cycles Register value 00h One input clock cycles 80h 129 input clock cycles FEh 255 input clock cycles FFh 256 input clock cycles
When the register value is set to "FF", the PWM signal is always "1".
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CHAPTER 21 SOUND GENERATOR
21.2.4 Decrement Grade Register
The Decrement Grade register stores the reload value for the Decrement counter. They are prepared to automatically decrement the stored value in the Amplitude Data register.
s Decrement Grade Register
Decrement Grade register Address: 001948H 7 D7 Read/write Initial value (R/W) (X) 6 D6 (R/W) (X) 5 D5 (R/W) (X) 4 D4 (R/W) (X) 3 D3 (R/W) (X) 2 D2 (R/W) (X) 1 D1 (R/W) (X) 0 D0 (R/W) (X) Bit number SGDR
When the DEC bit is "1" and the Decrement counter counts the number of tone pulses up to the reload value, the stored value in the Amplitude Data register is decremented by 1(one) at the end of the tone cycle. This operation realizes automatic de-gradation of the sound with fewer number of CPU interventions. It should be noted that the number of the tone pulses specified by this register equals to "register value +1". When the Decrement Grade register is set to "00", the decrement operation is performed every tone cycle.
334
21.2 Sound Generator Registers
21.2.5 Tone Count Register
The Tone Count register stores the reload value for the Tone Pulse counter. The Tone Pulse counter accumulate the number of tone pulses (or number of decrement operations) and when it reaches the reload value it sets the INT bit. They are intended to reduce the frequency of interrupts.
s Tone Count Register
Tone Count register Address: 001949H
15 D7
14 D6 (R/W) (X)
13 D5 (R/W) (X)
12 D4 (R/W) (X)
11 D3 (R/W) (X)
10 D2 (R/W) (X)
9 D1 (R/W) (X)
8 D0 (R/W) (X)
Bit number SGTR
Read/write Initial value
(R/W) (X)
The count input of the Tone Pulse counter is connected to the carry-out signal from the Decrement counter. And when the Tone count register is set to "00", the Tone Pulse counter sets the INT bit every carry-out from the Decrement counter. Thus the number of accumulated tone pulses is; ((Decrement Grade register) +1) x ((Tone Count register) +1) i.e. When the both registers are set to "00", the INT bit is set every tone cycle.
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CHAPTER 21 SOUND GENERATOR
336
CHAPTER 22
ROM CORRECTION
This chapter explains the functions and operations of ROM correction. 22.1 Outline of ROM Correction 22.2 Application Example of ROM Correction
337
CHAPTER 22 ROM CORRECTION
22.1 Outline of ROM Correction
When the setting of the address is the same as the ROM Correction Address registers, the INT9 instruction will be executed. By processing the INT9 interrupt service routine, the ROM correction function can be achieved. There are two address registers, in each containing a compare enable bit. When the address register and the program counter are in agreement, and when the compare enable bit is at '1', then the CPU will be forced to execute INT9 instruction.
s Block Diagram of ROM Correction Figure 22.1-1 shows a block diagram of the ROM correction. Figure 22.1-1 Block Diagram of ROM Correction
address latch comparitor ROM correction address register enable bit F2 MC-16 LX CPU core
INT9 instruction
F2MC-16LX BUS
s ROM Correction Address Register 0/1 (PADR0/PADR1) These registers hold the addresses for the comparison with program counter. If there is an agreement and when the corresponding ADCSR compare enable bit is at '1', this module demands the CPU to execute the INT9 instruction. If the corresponding compare enalble bit is '0', nothing will occur even there is a match.
byte PADR0 1FF2H/1FF1H/1FF0H PADR1 1FF5H/1FF4H/1FF3H
byte
byte
access initial value R/W R/W undefined undefined
338
22.1 Outline of ROM Correction The correspondance to the PACSR will be as follows. ROM Correction Address register PADR0 AD0E s ROM Correction Control Register (PACSR) The correspondence with PACSR is shown below. Compare enable bit PADR1 AD1E
ROM Correction Control Register Address : 009EH
Read/write Initial value
7
6
5
4
3 AD1E
(R/W) (0)
2
Reserved (R/W) (0)
1 AD0E
(R/W) (0)
0
Reserved (R/W) (0)
Bit number
Reserved Reserved Reserved Reserved (-) (0) (-) (0) (-) (0) (-) (0)
PACSR
This register controls operation of the address detect function and indicates its status. [bit 7~4] These are the reserved bits, be sure to write '0'. [bit 3]: AD1E (Compare Enable 1) This is the PADR1 enable bit. When this bit is at '1', this module compares the PADR1 register and the program counter. If there is an agreement, the INT9 instruction is sent to the CPU. [bit 2]: Reserved bit. [bit 1]: AD0E (Compare Enable 0) This is the PADR0 enable bit. When this bit is at '1', this module compares the PADR0 register and the program counter. If there is an agreement, the INT9 instruction is sent to the CPU. [bit 0]: Reserved bit. s Operations of ROM Correction When the program counter indicates the same address as the ROM Correction Address register, the INT9 instruction will be executed. By processing the INT9 interrupt service routine, the ROM correction function can be achieved. There are two address registers, in each containing a compare enable bit. When the address register and the program counter are in agreement, and when the compare enable bit is at '1', then the CPU will be forced to execute INT9 instruction. Note: When the address register and the program counter are in agreement, the internal data bus content will be forced to be '01H', so INT9 instruction will be executed. Before changing the content of the address register, make sure the compare enable bit is at '0'. If it is changed while the compare enable bit is at '1', there will occur an error.
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CHAPTER 22 ROM CORRECTION
22.2 Application Example of ROM Correction
The ROM correction function is enabled by externally providing an EEPROM and by storing information on corrections and a patch program in the EEPROM. Based on the correction information stored in the EEPROM, the CPU sets addresses requiring corrections in the ROM correction module and transfers the patch program to RAM. The processing can be transferred to the patch program by executing the INT9 instruction after address match detection.
s System Structure
Figure 22.2-1 System Structure Example
EPROM MCU F2 MC16LX
pull up resistor SIN connector (UART)
s EEPROM Memory Map address: content 0000H: number of bytes of the corrected program No. 0 (0 implies no ROM correction) 0001H: bit 7-0 program address No. 0 0002H: bit 15-8 program address No. 0 0003H: bit 24-16 program address No. 0 0004H: number of bytes of the corrected program No. 1 (0 implies no ROM correction) 0005H: bit 7-0 program address No. 1 0006H: bit 15-8 program address No. 1 0007H: bit 24-16 program address No. 1 0010H~: corrected program No. 0/1 body s Initial Condition EEPROM all at '0'.
340
22.2 Application Example of ROM Correction
22.2.1 Correction Example of Program Errors
Send the body of the corrected program and the program address to the MCU through the connector (UART). MCU then writes that information into the EEPROM.
s When a Program Error Occurs Figure 22.2-2 shows an example of ROM correction processing when a program error occurs. Figure 22.2-2 ROM Correction Processing Example
FFFFFFh
(3)
Erroneous Program ROM
(1) PC= Trigger Address
External E2PROM
Register setting for ROM correction
O Number of program byte O Interrupt Trigger Address O Corrected program
Data sent via UART RAM
(2)
Corrected programn
000000h
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CHAPTER 22 ROM CORRECTION
22.2.2 Example of Correction Processing
After resetting, the MCU reads the contents of the EEPROM. If the byte number of the corrected program is not '0', the body of the corrected program is read from the EEPROM and written in the RAM. Then the MCU sets the correction address either on PADR0 or on PADR1 and sets the compare enable bit. First address of the corrected program can written in the user-defined location of the RAM if a relocatable correction program is desired. In this case the INT9 service routine look for this user-defined location to jump to the corrected program.
s Reset Sequence
Figure 22.2-3 Processing Flow of ROM Correction
Reset
Read the 00h of E 2 PROM
YES
INT9 0000h (E2PROM)=0
NO Read the Address 0001h~0003h (E2PROM) MOV PADR0 (MCU)
To Corrected Program JMP 000400h
Read the corrected Program 0010h~0090h (E2PROM) MOV 000400h~000480h (MCU)
Corrected Program Execution 000400h~000480h
Enable compare MOV PACSR, #02h
End of Corrected Program JMP FF0050h
Normal Program Execution
NO PC=PADR0
YES INT9
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22.2 Application Example of ROM Correction Figure 22.2-4 ROM Correction Processing Flow Diagram
FFFFFFh E2 PROM FFFFh ROM 0090h
Corrected Program
FF0050h
Erroneous Program
FF0000h FE0000h 001100h
Lower Program Address: 00 Stack Area RAM Area
0010h
0003h
Middle Program Address: 00
0002h
Upper Program Address: FF
RAM
000480h
Corrected Program
0001h
Size of Corrected Program in Byte
000400h
RAM/Register Area
0000h : 80
000100h
I/O Area
000000h
s INT9 Interrupt In the interrupt routine, the address that produces the interrupt can be known by checking the stacked program counter value. The information stacked during interrupt will be discarded.
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CHAPTER 22 ROM CORRECTION
344
CHAPTER 23
ROM MIRRORING MODULE
This chapter explains the ROM mirroring module. 23.1 Outline of ROM Mirroring Module 23.2 ROM Mirroring Register (ROMM)
345
CHAPTER 23 ROM MIRRORING MODULE
23.1 Outline of ROM Mirroring Module
The ROM Mirroring module switches whether to mirror the image of the FF bank of the ROM to the 00 bank.
s Block Diagram of ROM Mirroring Module
Figure 23.1-1 Block Diagram of ROM Mirroring Module
F2MC-16LX BUS
ROM Mirrroring Register
Address Area
FF bank 00 bank
ROM
346
23.2 ROM Mirroring Register (ROMM)
23.2 ROM Mirroring Register (ROMM)
Do not access the ROM mirroring register (ROMM) when addresses 004000H to 00FFFFH are being accessed.
s ROM Mirroring Register (ROMM)
15 Address : 0006F H
Read/write Initial value
14 --
(-) (-)
13 --
(-) (-)
12 --
(-) (-)
11 --
(-) (-)
10 --
(-) (-)
9 --
(-) (-)
8 MI
(W) (1)
Bit number
--
(-) (-)
ROMM
[bit 8] : MI The image of the ROM data in the FF bank can also be found in the 00 bank when '1' is written to this bit. However, this memory mapping will not be done when this bit is written to '0'. This bit is write only. Note: Only FF4000~FFFFFF is mirrorred to 004000~00FFFF when ROM mirroring functing is activated. Therefore, addresses FFF000~FF3FFF will not be mirrorred to 00 bank.
347
CHAPTER 23 ROM MIRRORING MODULE
348
CHAPTER 24
2M/3M-BIT FLASH MEMORY
This chapter describes the functions and operation of the 2M/3M-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: * Parallel writer (Minato Electronics Model 1890A) * Serial writer (Yokogawa Digital Computer Model AF-200) * Executing programs to write/erase data This chapter elaborates on Chapter 3, "Executing Programs to Write/Erase Data." 24.1 Outline of 2M/3M-Bit Flash Memory 24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory 24.3 Write/Erase Modes 24.4 Flash Memory Control Status Register (FMCS) 24.5 Starting the Flash Memory Automatic Algorithm 24.6 Confirming the Automatic Algorithm Execution State 24.7 Detailed Explanation of Writing to and Erasing Flash Memory 24.8 Notes on Using 2M/3M-Bit Flash Memory 24.9 Reset Vector Address in Flash Memory 24.10 Example of Programming 2M/3M-Bit Flash Memory
349
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.1 Outline of 2M/3M-Bit Flash Memory
The 2M/3M-bit flash memory is mapped to the FC to FF bank in the CPU memory map. The functions of the flash memory interface circuit enable read-access and programaccess from the CPU in the same way as mask ROM. Instructions from the CPU can be used via the flash memory interface circuit to write data to and erase data from the flash memory. Internal CPU control therefore enables rewriting of the flash memory while it is mounted. As a result, improvements in programs and data can be performed efficiently. Selector operations such as enable selector protect cannot be used.
s 2M/3M-bit Flash Memory Features * * * * * * * Use of automatic program algorithm (Embedded Algorithm: Equivalent to MBM29F400TA) Erase pause/restart functions provided Detection of completion of writing/erasing using data polling or toggle bit functions Detection of completion of writing/erasing using CPU interrupts Compatible with JEDEC standard commands Sector erase function (any combination of sectors) Minimum of 10,000 write/erase operations
Embedded Algorithm is a trademark of Advanced Micro Device, Inc. s Writing to/Erasing Flash Memory The flash memory cannot be written to and read at the same time. That is, when data is written to or erased data from the flash memory, the program in the flash memory must first be copied to RAM. The entire process is then executed in RAM so that data is simply written to the flash memory. This eliminates the need for the program to access the flash memory from the flash memory itself. s Flash Memory Register
r Flash Memory Control Status Register (FMCS)
7 Address: 0000AEH Read/write Initial value INTE (R/W) (0)
6 RDYINT (R/W) (0)
5 WE (R/W) (0)
4 RDY (R) (X)
3 Reserved (R/W) (0)
2 LPM1 (R/W) (0)
1 Reserved (R/W) (0)
0 LPM0 (R/W) (0)
Bit No. FMCS
350
24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory
24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory
Figure 24.2-1 shows a block diagram of the entire flash memory with the flash memory interface circuit included. Figure 24.2-2 shows the sector configuration of the flash memory.
s Block Diagram of the Entire Flash Memory
Figure 24.2-1 Block Diagram of the Entire Flash Memory
Flash memory interface circuit 2Mbit/3Mbit Flash memory BYTE CE OE WE AQ0 to AQ17 AQ-1 DQ0 to DQ15 RY/BY RESET Write enable interrupt signal (to CPU)
BYTE Port 2 Port 3 Port 4 CE OE WE AQ0 to AQ18 DQ0 to DQ15 F2MC-16 bus INT RY/BY
External reset signal
RY/BY write enable signal
s Sector Configuration of the 2M/3M-Bit Flash Memory Figure 24.2-2 shows the sector configuration of the 2M/3M-bit flash memory. The addresses in the figure indicate the high-order and low-order addresses of each sector.
351
CHAPTER 24 2M/3M-BIT FLASH MEMORY Figure 24.2-2 Sector Configuration of the 2M/3M-Bit Flash Memory
MB90F594A
Writer address CPU address SA6 (16K bytes) SA5 (8K bytes) SA4 (8K bytes) SA3 (32K bytes) SA2 (64K bytes) SA1 (64K bytes) 4FFFFH SA0 (64K bytes) 40000H FC0000H FCFFFFH 7FFFFH 7BFFFH 79FFFH 77FFFH 6FFFFH 5FFFFH FFFFFFH FFBFFFH FF9FFFH FF7FFFH FEFFFFH FDFFFFH
MB90F591
Writer address CPU address SA11 (16K bytes) SA10 (8K bytes) SA8 (8K bytes) SA8 (32K bytes) SA7 (64K bytes) SA6 (64K bytes) 4FFFFH Unused 3FFFFH SA5 (16K bytes) 3BFFFH SA4 (8K bytes) 39FFFH SA3 (8K bytes) 37FFFH SA2 (32K bytes) 2FFFFH SA1(64K bytes) 1FFFFH SA0 (64K bytes) 0FFFFH Unused 00000H F80000H F8FFFFH F9FFFFH FAFFFFH FB7FFFH FB9FFFH FBBFFFH FBFFFFH FCFFFFH 7FFFFH 7BFFFH 79FFFH 77FFFH 6FFFFH 5FFFFH FFFFFFH FFBFFFH FF9FFFH FF7FFFH FEFFFFH FDFFFFH
*: The writer address is equivalent to the CPU address when data is written to the flash memory using a parallel writer. When a general writer is used for writing/erasing, this address is used for writing/erasing.
352
24.3 Write/Erase Modes
24.3 Write/Erase Modes
The flash memory can be accessed in two different ways: Flash memory mode and alternative mode. Flash memory mode enables data to be directly written to or erased from the external pins. Alternative mode enables data to be written to or erased from the CPU via the internal bus. Use the mode external pins to select the mode.
s Flash Memory Mode The CPU stops when the mode pins are set to 111 while the reset signal is asserted. The flash memory interface circuit is connected directly to ports 0, 2, 3, and 4, enabling direct control from the external pins. This mode makes the MCU seem like a standard flash memory to the external pins, and write/erase can be performed using a flash memory programmer. In flash memory mode, all operations supported by the flash memory automatic algorithm can be used. s Alternative Mode The flash memory is located in the FC to FF banks in the CPU memory space, and like ordinary mask ROM, can be read-accessed and program-accessed from the CPU via the flash memory interface circuit. Since writing/erasing the flash memory is performed by instructions from the CPU via the flash memory interface circuit, this mode allows rewriting even when the MCU is soldered on the target board. Sector protect operations cannot be performed in these modes. s Flash Memory Control Signals Table 24.3-1 lists the flash memory control signals in flash memory mode. There is almost a one-to-one correspondence between the flash memory control signals and the external pins of the MBM29F400TA. The VID (12 V) pins required by the sector protect operations are MD0, MD1, and MD2 instead of A9, RESET, and OE for the MBM29F400TA. Since the memory capacity of the MB90F594A is half of the MBM29F400TA, the AQ18 pin corresponding to the address signal A17 of the MBM29F400TA is redundant. These pins should always be set to 1. In flash memory mode, the external data bus signal width is limited to 8 bits, enabling only onebyte access. The DQ15 to DQ18 pins are not supported. The BYTE pin should always be set to 0. Table 24.3-1 Flash Memory Control Signals MB90F594A/MB90F591 MBM29F400TA Pin number 1 to 8 9 10 Normal function P20 to P27 P30 P31 Flash memory mode AQ0 to AQ7 AQ16 CE A-1, A0 to A6 A15 CE
353
CHAPTER 24 2M/3M-BIT FLASH MEMORY Table 24.3-1 Flash Memory Control Signals (Continued) MB90F594A/MB90F591 MBM29F400TA Pin number 12 13 14 to 15 16 17 18 to 22 24 to 26 49 50 51 85 to 92 77 Normal function P32 P33 P34 to P35 P36 P37 P40 to P44 P45 to P47 MD0 MD1 MD2 P00 to P07 RST Not supported Flash memory mode OE WE AQ17 to AQ18 BYTE RY/BY AQ8 to AQ12 AQ13 to AQ15 MDO MD1 MD2 DQ0 to DQ7 RESET OE WE A16 to A17 BYTE RY/BY A7 to A11 A12 to A14 A9 (VID) RESET (VID) OE (VID) DQ0 to DQ7 RESET DQ8 to DQ15
354
24.4 Flash Memory Control Status Register (FMCS)
24.4 Flash Memory Control Status Register (FMCS)
The flash memory control status register (FMCS), together with the flash memory interface circuit, is used to write data to and erase data from the flash memory.
s Flash Memory Control Status Register (FMCS)
7 Address: 0000AEH Read/write Initial value INTE (R/W) (0)
6 RDYINT (R/W) (0)
5 WE (R/W) (0)
4 RDY (R) (1)
3 Reserved (R/W) (0)
2 LPM1 (R/W) (0)
1 Reserved (R/W) (0)
0 LPM0 (R/W) (0)
Bit No. FMCS
r Explanation of bits [Bit 7] INTE (interrupt enable) This bit generates an interrupt to the CPU when flash memory write/erase terminates. An interrupt to the CPU is generated when the INTE and RDYINT bits are 1. No interrupt is generated when the INTE bit is 0. * * 0: Disables interrupts when write/erase terminates. 1: Enables interrupts when write/erase terminates.
[Bit 6] RDYINT (ready interrupt) This bit indicates the operating state of the flash memory. This bit is set to 1 when flash memory write/erase terminates. Data cannot be written to or erased from the flash memory while this bit is 0 after a flash memory write/erase. Flash memory write/erase is enabled when write/erase terminates and this bit is set to 1. Writing 0 clears this bit to 0. Writing 1 is ignored. This bit is set to 1 at the termination timing of the flash memory automatic algorithm (see Section 1.4, "Starting the Flash Memory Automatic Algorithm"). When the read-modify-write (RMW) instruction is used, 1 is always read. * * 0: Write/erase is being executed. 1: Write/erase has terminated (interrupt request generated).
[Bit 5] WE (write enable) This bit enables writing to the flash memory area. When this bit is 1, writing after the command sequence (see Section 1.4, "Starting the Flash Memory Automatic Algorithm") is issued to the FC to FF bank writes to the flash memory area. When this bit is 0, the write/erase signal is not generated. This bit is used when the flash memory Write/Erase command is started. If write/erase is not performed, it is recommended that this bit be set to 0 to prevent data from being mistakenly written to the flash memory. * 0: Disables flash memory write/erase.
355
CHAPTER 24 2M/3M-BIT FLASH MEMORY * 1: Enables flash memory write/erase.
[Bit 4] RDY (ready) This bit enables flash memory write/erase. Flash memory write/erase is disabled while this bit is 0. However, Suspend commands, such as the Read/Reset command and Sector Erase Suspend command, can be accepted even if this bit is 0. * * 0: Write/erase is being executed. 1: Write/erase has terminated (next data write/erase enabled).
[Bits 3 and 1] Reserved bits These bits are reserved for testing. During regular use, they should always be set to 0. [Bits 2 and 0] LPM1 and LPM0 (low power mode) These bits control the current consumed by the flash memory when the flash memory is accessed. Since the access time to the flash memory from the CPU is largely dependent on this setting, select a setting value based on the operating frequency of the CPU. * * * * 01: Low power consumption mode (Operates at an internal operating frequency up to 4 MHz.) 10: Low power consumption mode (Operates at an internal operating frequency up to 8 MHz.) 11: Low power consumption mode (Operates at an internal operating frequency up to 10 MHz.) 00: Regular power consumption mode (Operates at an internal operating frequency up to 16 MHz.)
Note: The RDYINT and RDY bits cannot be changed at the same time. Create a program so that decisions are made using one or the other of these bits.
Automatic algorithm Termination timing RDYINT bit RDY bit
1 machine cycle
356
24.5 Starting the Flash Memory Automatic Algorithm
24.5 Starting the Flash Memory Automatic Algorithm
Four types of commands are available for starting the flash memory automatic algorithm: Read/Reset, Write, and Chip Erase. Control of suspend and restart is enabled for sector erase.
s Command Sequence Table Table 24.5-1 lists the commands used for flash memory write/erase. All of the data written to the command register is in bytes, but use word access to write. The data of the high-order bytes at this time is ignored. Table 24.5-1 Command Sequence Table
Command sequence Bus write access 1st bus write cycle 2nd bus write cycle Address Data 3rd bus write cycle Address Data 4th bus write cycle Address Data 5th bus write cycle Address Data 6th bus write cycle Address Data -
Address Read/Reset (*1) Read/Reset (*1) Write program Chip Erase Sector Erase 1 FxXXXX
Data XXF0
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXF0
RA PA (even) FxAAAA FxAAAA
RD PD (word) XXAA XXAA
-
-
-
-
4 6 6
FxAAAA FxAAAA FxAAAA
XXAA XXAA XXAA
Fx5554 Fx5554 Fx5554
XX55 XX55 XX55
FxAAAA FxAAAA FxAAAA
XXA0 XX80 XX80
Fx5554 Fx5554
XX55 XX55
FxAAAA SA (even)
XX10 XX30
Sector Erase Suspend Sector Erase Restart
Entering address FxXXXX data (xxBOH) suspends erasing during sector erase. Entering address FxXXXX data (xx3OH) restarts erasing after erasing is suspended during sector erase.
Notes: * * * * * * * The addresses Fx in the table mean FF, FE, FD, and FC. Use these addresses as the access target bank values for operations. The addresses in the table are the values in the CPU memory map. All addresses and data are represented using hexadecimal notation. However, the letter X is an optional value. RA: Read address PA: Write address. Only even addresses can be specified. SA: Sector address. See Section 1.2, "2M/3M-Bit Flash Memory Sector Configuration." RD: Read data PD: Write data. Only word data can be specified.
*1 Both of the two types of Read/Reset commands can reset the flash memory to read mode.
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CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.6 Confirming the Automatic Algorithm Execution State
Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm enables confirmation of the operating state of the built-in flash memory using the following hardware sequences.
s Hardware Sequence Flags The hardware sequence flags are configured from the four-bit output of DQ7, DQ6, DQ5, and DQ3. The functions of these bits are those of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit exceeded flag (DQ5), and sector erase timer flag (DQ3). The hardware sequence flags can therefore be used to confirm that writing or chip sector erase has been completed or that erase code write is valid. The hardware sequence flags can be accessed by read-accessing the addresses of the target sectors in the flash memory after setting of the command sequence (see Table 24.5-1 in Section 24.5, "Starting the Flash Memory Automatic Algorithm"). Table 24.6-1 lists the bit assignments of the hardware sequence flags. Table 24.6-1 Bit Assignments of Hardware Sequence Flags Bit No. Hardware sequence flag 7 DQ7 6 DQ6 5 DQ5 4 3 DQ3 2 1 0 -
To determine whether automatic writing or chip sector erase is being executed, the hardware sequence flags can be checked or the status can be determined from the RDY bit of the flash memory control register (FMCS) that indicates whether writing has been completed. After writing/erasing has terminated, the state returns to the read/reset state. When creating a program, use one of the flags to confirm that automatic writing/erasing has terminated. Then, perform the next processing operation, such as data read. In addition, the hardware sequence flags can be used to confirm whether the second or subsequent sector erase code write is valid. The following sections describe each hardware sequence flag separately. Table 24.6-2 lists the functions of the hardware sequence flags.
358
24.6 Confirming the Automatic Algorithm Execution State Table 24.6-2 Hardware Sequence Flag Functions State State change for normal operation Write --> Write completed (write address specified) Chip/sector erase --> Erase completed Sector erase wait --> Erase started Erase --> Sector erase suspended (sector being erased) Sector erase suspend --> Erase restarted (sector being erased) Sector erase suspended (sector not being erased) Abnormal operation Write Chip/sector erase DQ7 DQ7 --> DATA:7 0 --> 1 0 0 --> 1 1 --> 0 DATA:7 DQ7 0 DQ6 Toggle --> DATA:6 Toggle --> Stop Toggle Toggle --> 1 1 --> Toggle DATA:6 Toggle Toggle DQ5 0 --> DATA:5 0 --> 1 0 0 0 DATA:5 1 1 DQ3 0 --> DATA:3 1 0 --> 1 1 --> 0 0 --> 1 DATA:3 0 1
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CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.6.1 Data Polling Flag (DQ7)
The data polling flag (DQ7) uses the data polling function to post that the automatic algorithm is being executed or has terminated
s Data Polling Flag (DQ7) Tables 24.6-3 and 24.6-4 list the state transitions of the data polling flag. Table 24.6-3 Data Polling Flag State Transitions (State Change for Normal Operation) Chip/sector erase --> Completed 0 --> 1 Sector erase wait --> Started 0 Sector erase --> Erase suspend (sector being erased) 0 --> 1 Sector erase suspend --> Restarted (sector being erased) 1 --> 0 Sector erase suspended (sector not being erased) DATA:7
Operating state
Write --> Completed
DQ7
DQ7 -->
Table 24.6-4 Data Polling Flag State Transitions (State Change for Abnormal Operation) Operating state DQ7 r Write Read-access during execution of the automatic write algorithm causes the flash memory to output the opposite data of bit 7 last written, regardless of the value at the address specified by the address signal. Read-access at the end of the automatic write algorithm causes the flash memory to output bit 7 of the read value of the address specified by the address signal. r Chip/sector erase For a sector erase, read-access during execution of the chip erase/sector erase algorithm causes the flash memory to output 0 from the sector currently being erased. For a chip erase, read-access causes the flash memory to output 0 regardless of the value at the address specified by the address signal. Read-access at the end of the automatic write algorithm causes the flash memory to output 1 in the same way. r Sector erase suspend Read-access during a sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit 7 (DATA: 7) of the read value at the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. Referencing this flag together with the toggle bit flag (DQ6) enables a decision to be made on whether the flash memory is in the erase suspended state and which sector is being erased. Note: When the automatic algorithm is being started, read-access to the specified address is ignored. Since termination of the data polling flag (DQ7) can be accepted for a data read 360 Write DQ7 Chip/sector erase 0
24.6 Confirming the Automatic Algorithm Execution State and other bits output, data read after the automatic algorithm has terminated should be performed after read-access has confirmed that data polling has terminated.
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CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.6.2 Toggle Bit Flag (DQ6)
Like the data polling flag, the toggle bit flag (DQ6) uses the toggle bit function to post that the automatic algorithm is being executed or has terminated.
s Toggle Bit Flag (DQ6) Tables 24.6-5 and 24.6-6 list the state transitions of the toggle bit flag. Table 24.6-5 Toggle Bit Flag State Transitions (State Change for Normal Operation) Chip/sector erase --> Completed Toggle --> Stop Sector erase wait --> Started Sector erase --> Erase suspend (sector being erased) Toggle --> 1 Sector erase suspend --> Restarted (sector being erased) 1 --> Toggle Sector erase suspended (sector not being erased) DATA:6
Operating state
Write --> Completed
DQ6
Toggle --> DATA:6
Toggle
Table 24.6-6 Toggle Bit Flag State Transitions (State Change for Abnormal Operation) Operating state DQ6 Write Toggle Chip/sector erase Toggle
r Write/chip sector erase Continuous read-access during execution of the automatic write algorithm and chip/sector erase algorithm causes the flash memory to toggle the 1 or 0 state for every read cycle, regardless of the value at the address specified by the address signal. Continuous read-access at the end of the automatic write algorithm and chip/sector erase algorithm causes the flash memory to stop toggling bit 6 and output bit 6 (DATA: 6) of the read value of the address specified by the address signal. r Sector erase suspend Read-access during a sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit 6 (DATA: 6) of the read value at the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. For a write, if the sector where data is to be written is rewrite-protected, the toggle bit terminates the toggle operation after approximately 2s without any data being rewritten. For an erase, if all of the selected sectors are write-protected, the toggle bit performs toggling for approximately 100s and then returns to the read/reset state without any data being rewritten.
362
24.6 Confirming the Automatic Algorithm Execution State
24.6.3 Timing Limit Exceeded Flag (DQ5)
The timing limit exceeded flag (DQ5) is used to post that execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in the flash memory.
s Timing Limit Exceeded Flag (DQ5) Tables 24.6-7 and 24.6-8 list the state transitions of the timing limit exceeded flag. Table 24.6-7 Timing Limit Exceeded Flag State Transitions (State Change for Normal Operation) Chip/sector erase --> Completed 0 --> 1 Sector erase wait --> Started 0 Sector erase --> Erase suspend (sector being erased) 0 Sector erase suspend --> Restarted (sector being erased) 0 Sector erase suspended (sector not being erased) DATA:5
Operating state
Write --> Completed
DQ5
0 --> DATA:5
Table 24.6-8 Timing Limit Exceeded Bit Flag State Transitions (State Change for Abnormal Operation) Operating state DQ5 Write 1 Chip/sector erase 1
r Write/chip sector erase Read-access after write or chip/sector erase automatic algorithm activation causes the flash memory to output 0 if the time is within the prescribed time (time required for write/erase) or to output 1 if the prescribed time has been exceeded. Because this is done regardless of whether the automatic algorithm is being executed or has terminated, it is possible to determine whether write/erase was successful or unsuccessful. That is, when this flag outputs 1, writing can be determined to have been unsuccessful if the automatic algorithm is still being executed by the data polling function or toggle bit function. For example, writing 1 to a flash memory address where 0 has been written will cause the fail state to occur. In this case, the flash memory will lock and execution of the automatic algorithm will not terminate. As a result, valid data will not be output from the data polling flag (DQ7). In addition, the toggle bit flag (DQ6) will exceed the time limit without stopping the toggle operation and the timing limit exceeded flag (DQ5) will output 1. Note that this state indicates that the flash memory is not faulty, but has been used correctly. When this state occurs, execute the Reset command.
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CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.6.4 Sector Erase Timer Flag (DQ3)
The sector erase timer flag (DQ3) is used to post whether the automatic algorithm is being executed during the sector erase wait period after the Sector Erase command has been started.
s Sector Erase Timer Flag (DQ3) Tables 24.6-9 and 24.6-10 list the state transitions of the sector erase timer flag. Table 24.6-9 Sector Erase Timer Flag State Transitions (State Change for Normal Operation) Sector erase --> Erase suspend (sector being erased) 1 --> 0 Sector erase suspend --> Restarted (sector being erased) 0 --> 1 Sector erase suspended (sector not being erased) DATA:3
Operating state
Write --> Completed
Chip/sector erase --> Completed 1
Sector erase wait --> Started 0 --> 1
DQ3
0 --> DATA:3
Table 24.6-10 Sector Erase Timer Flag State Transitions (State Change for Abnormal Operation) Operating state DQ3 r Sector erase Read-access after the Sector Erase command has been started causes the flash memory to output 0 if the automatic algorithm is being executed during the sector erase wait period, regardless of the value at the address specified by the address signal of the sector that issued the command. The flash memory outputs 1 if the sector erase wait period has been exceeded. If the data polling function or toggle bit function indicates that the erase algorithm is being executed, internally controlled erase has already started if this flag is 1. Continuous write of the sector erase codes or commands other than the Sector Erase Suspend command will be ignored until erase is terminated. If this flag is 0, the flash memory will accept write of additional sector erase codes. To confirm this, it is recommended that the state of this flag be checked before continuing to write sector erase codes. If this flag is 1 after the second state check, it is possible that additional sector erase codes may not be accepted. r Sector erase Read-access during execution of sector erase suspend causes the flash memory to output 1 if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit 3 (DATA: 3) of the read value of the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. Write 0 Chip/sector erase 1
364
24.7 Detailed Explanation of Writing to and Erasing Flash Memory
24.7 Detailed Explanation of Writing to and Erasing Flash Memory
This section describes each operation procedure of flash memory Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a command that starts the automatic algorithm is issued.
s Detailed Explanation of Flash Memory Write/Erase The flash memory executes the automatic algorithm by issuing a command sequence (see Table 24.5-1 in Section 24.5, "Starting the Flash Memory Automatic Algorithm") for a write cycle to the bus to perform Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, or Sector Erase Restart operations. Each bus write cycle must be performed continuously. In addition, whether the automatic algorithm has terminated can be determined using the data polling or other function. At normal termination, the flash memory is returned to the read/reset state. Each operation of the flash memory is described in the following order: * * * * * * Setting the read/reset state Writing data Erasing all data (erasing chips) Erasing optional data (erasing sectors) Suspending sector erase Restarting sector erase
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CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.7.1 Setting The Read/Reset State
This section describes the procedure for issuing the Read/Reset command to set the flash memory to the read/reset state.
s Setting the Flash Memory to the Read/Reset State The flash memory can be set to the read/reset state by sending the Read/Reset command in the command sequence table (see Table 24.5-1 in Section 24.5, "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Read/Reset command has two types of command sequences that execute the first and third bus operations. However, there are no essential differences between these command sequences. The read/reset state is the initial state of the flash memory. When the power is turned on and when a command terminates normally, the flash memory is set to the read/reset state. In the read/reset state, other commands wait for input. In the read/reset state, data is read by regular read-access. As with the mask ROM, program access from the CPU is enabled. The Read/Reset command is not required to read data by a regular read. The Read/Reset command is mainly used to initialize the automatic algorithm in such cases as when a command does not terminate normally.
366
24.7 Detailed Explanation of Writing to and Erasing Flash Memory
24.7.2 Writing Data
This section describes the procedure for issuing the Write command to write data to the flash memory.
s Writing Data to the Flash Memory The data write automatic algorithm of the flash memory can be started by sending the Write command in the command sequence table (see Table 24.5-1 in Section 24.5, "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. When data write to the target address is completed in the fourth cycle, the automatic algorithm and automatic write are started. r Specifying addresses Only even addresses can be specified as the write addresses specified in a write data cycle. Odd addresses cannot be written correctly. That is, writing to even addresses must be done in units of word data. Writing can be done in any order of addresses or even if the sector boundary is exceeded. However, the Write command writes only data of one word for each execution. r Notes on writing data Writing cannot return data 0 to data 1. When data 1 is written to data 0, the data polling algorithm (DQ7) or toggle operation (DQ6) does not terminate and the flash memory elements are determined to be faulty. If the time prescribed for writing is thus exceeded, the timing limit exceeded flag (DQ6) is determined to be an error. Otherwise, the data is viewed as if dummy data 1 had been written. However, when data is read in the read/reset state, the data remains 0. Data 0 can be set to data 1 only by erase operations. All commands are ignored during execution of the automatic write algorithm. If a hardware reset is started during writing, the data of the written addresses will be unpredictable. s Writing to the Flash Memory Figure 24.7-1 is an example of the procedure for writing to the flash memory. The hardware sequence flags (see Section 24.6, "Confirming the Automatic Algorithm Execution State") can be used to determine the state of the automatic algorithm in the flash memory. Here, the data polling flag (DQ7) is used to confirm that writing has terminated. The data read to check the flag is read from the address written to last. The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5) changes. For example, even if the timing limit exceeded flag (DQ5) is 1, the data polling flag bit (DQ7) must be rechecked. Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timing limit exceeded flag bit (DQ5) changes to 1. The toggle bit flag (DQ6) must therefore be rechecked.
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CHAPTER 24 2M/3M-BIT FLASH MEMORY Figure 24.7-1 Example of the Flash Memory Write Procedure
Start writing
FMCS: WE (bit 5) Enable flash memory write
Write command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XXA0 (4) Write address <-- Write data Read internal address
Next address
Data polling (DQ7)
Data
Data 0
Timing limit (DQ5)
1
Read internal address
Data
Data polling (DQ7)
Data
Write error
Final address
FMCS: WE (bit 5) Disable flash memory write Confirm with the hardware sequence flags.
Complete writing
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24.7 Detailed Explanation of Writing to and Erasing Flash Memory
24.7.3 Erasing All Data (Erasing Chips)
This section describes the procedure for issuing the Chip Erase command to erase all data in the flash memory.
s Erasing all Data in the Flash Memory (Erasing Chips) All data can be erased from the flash memory by sending the Chip Erase command in the command sequence table (see Table 24.5-1 in Section 24.5, "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Chip Erase command is executed in six bus operations. When writing of the sixth cycle is completed, the chip erase operation is started. For chip erase, the user need not write to the flash memory before erasing. During execution of the automatic erase algorithm, the flash memory writes 0 for verification before all of the cells are erased automatically.
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CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.7.4 Erasing Optional Data (Erasing Sectors)
This section describes the procedure for issuing the Sector Erase command to erase optional data (erase sector) in the flash memory. Individual sectors can be erased. Multiple sectors can also be specified at one time.
s Erasing Optional Data (Erasing Sectors) in the Flash Memory Optional sectors in the flash memory can be erased by sending the Sector Erase command in the command sequence table (see Table 24.5-1 in Section 24.5, "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. r Specifying sectors The Sector Erase command is executed in six bus operations. Sector erase wait of 50s is started by writing the sector erase code (30h) to an accessible even-numbered address in the target sector in the sixth cycle. To erase multiple sectors, write the erase code (30h) to the addresses in the target sectors after the above processing operation. r Notes on specifying multiple sectors Erase is started when the sector erase wait period of 50s terminates after the final sector erase code has been written. That is, to erase multiple sectors at one time, an erase code (sixth cycle of the command sequence) must be written within 50s of writing of the address of a sector and the address of the next sector must be written within 50s of writing of the previous erase code. Otherwise, the address and erase code may not be accepted. The sector erase timer (hardware sequence flag DQ3) can be used to check whether writing of the subsequent sector erase code is valid. At this time, specify so that the address used for reading the sector erase timer indicates the sector to be erased. s Erasing Sectors in the Flash Memory The hardware sequence flags (see Section 1.5, "Referencing the Automatic Algorithm Execution State") can be used to determine the state of the automatic algorithm in the flash memory. Figure 24.7-2 is an example of the procedure for erasing sectors in the flash memory. Here, the toggle bit flag (DQ6) is used to confirm that erasing has terminated. The data that is read to check the flag is read from the sector to be erased. The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limit exceeded flag (DQ5) is changed to 1. For example, even if the timing limit exceeded flag (DQ5) is 1, the toggle bit flag (DQ6) must be rechecked. The data polling flag (DQ7) also changes at the same time that the timing limit exceeded flag bit (DQ5) changes. As a result, the data polling flag (DQ7) must be rechecked.
370
24.7 Detailed Explanation of Writing to and Erasing Flash Memory Figure 24.7-2 Example of the Flash Memory Sector Erase Procedure
Start erasing FMCS: WE (bit 5) Enable flash memory erase
Erase command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XX80 (4) FxAAAA <-- XXAA (5) Fx5554 <-- XX55
0
1
Sector erase timer (DQ3)
(6) Enter code to erase sector (30H)
Read internal address
Y
Another erase sector
N
Read internal address 1 Read internal address 2
Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6)
N 0 Y
Next sector
Timing limit (DQ5)
1
Read internal address 1 Read internal address 2
N
Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6)
Y
Erase error
Final sector
Y
N
FMCS: WE (bit 5) Disable flash memory erase Confirm with the hardware sequence flags. Complete erasing
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CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.7.5 Suspending Sector Erase
This section describes the procedure for issuing the Sector Erase Suspend command to suspend erasing of flash memory sectors. Data can be read from sectors that are not being erased.
s Suspending Erasing of Flash Memory Sectors Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspend command in the command sequence table (see Table 1 in Section 1.4, "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Sector Erase Suspend command suspends the sector erase operation being executed and enables data to be read from sectors that are not being erased. In this state, only reading is enabled; data cannot be written. This command is valid only during sector erase operations that include the erase wait time. The command will be ignored during chip erase or write operations. This command is implemented by writing the erase suspend code (B0h). At this time, specify an optional address in the flash memory for the address. An Erase Suspend command issued again during erasing of sectors will be ignored. Entering the Sector Erase Suspend command during the sector erase wait period will immediately terminate sector erase wait, cancel the erase operation, and set the erase stop state. Entering the Erase Suspend command during the erase operation after the sector erase wait period has terminated will set the erase suspend state after a maximum period of 15s has elapsed.
372
24.7 Detailed Explanation of Writing to and Erasing Flash Memory
24.7.6 Restarting Sector Erase
This section describes the procedure for issuing the Sector Erase Restart command to restart suspended erasing of flash memory sectors.
s Restarting Erasing of Flash Memory Sectors Suspended erasing of flash memory sectors can be restarted by sending the Sector Erase Restart command in the command sequence table (see Table 24.5-1 in Section 24.5, "Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Sector Erase Restart command is used to restart erasing of sectors from the sector erase suspend state set using the Sector Erase Suspend command. The Sector Erase Restart command is implemented by writing the erase restart code (30h). At this time, specify an optional address in the flash memory area for the address. If a Sector Erase Restart command is issued during sector erase, the command will be ignored.
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CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.8 Notes on using 2M-Bit Flash Memory
This section contains notes on using 2M-bit flash memory.
s Notes on using flash memory r Input of a hardware reset (RST) To input a hardware reset when the automatic algorithm has not been started and reading is in progress, a minimum low-level width of 500 ns must be maintained. In this case, a maximum of 500 ns is required until data can be read from the flash memory after a hardware reset has been activated. Similarly, to input a hardware reset when the automatic algorithm has been activated and writing or erasing is in progress, a minimum low-level width of 50 ns must be maintained. In this case, 20 (s are required until data can be read after the operation for initializing the flash memory has terminated. A hardware reset during writing the data being written to be undefined. A hardware reset during erasing may make the sector being erased unusable. r Canceling of a software reset, watchdog timer reset, and hardware standby When the flash memory is being written to or erased with CPU access and if reset conditions occur while the automatic algorithm is active, the CPU may run out of control. This occurs because these reset conditions cause the automatic algorithm to continue without initializing the flash memory unit, possibly preventing the flash memory unit from entering the read state when the CPU starts the sequence after the reset has been deasserted. These reset conditions must be disabled during writing to or erasing of the flash memory. r Program access to flash memory When the automatic algorithm is operating, read access to the flash memory is disabled. With the memory access mode of the CPU set to internal ROM mode, writing or erasing must be started after the program area is switched to another area such as RAM. In this case, when sectors (SA6) containing interrupt vectors are erased, writing or erasing interrupt processing cannot be executed. For the same reason, all interrupt sources other than the flash memory are disabled while the automatic algorithm is operating. Also, while the automatic algorithm is being executed, all interrupt sources except flash memory are disabled. r Hold function When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be skewed, causing erroneous writing or erasing due to an erroneous write. When the acceptance of a hold request is enabled (HDE bit of EPCR set to 1), ensure that the WE bit of the control status register (FMCS) is 0. r Extended intelligent I/O service (EI2OS) Because write and erase interrupts issued to the CPU from the flash memory interface circuit cannot be accepted by the EI2OS, they should not be used.
374
24.8 Notes on using 2M-Bit Flash Memory r Applying VID Applying VID required for the sector protect operation should always be started and terminated when the supply voltage is on.
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CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.9 Reset Vector Address in Flash Memory
The MB90F594A supports a hard-wired reset vector. When the addresses FFFFDCH to FFFFDFH are accessed for reading data in internal vector mode, the values that have been determined by the hard-wired logic in advance are read. However, in flash memory mode, as mentioned in the previous chapter, all addresses can be accessed. Consequently, it is meaningless to write data to these addresses. Especially when programming flash memory from the CPU (that is, not in flash memory mode), do not read these addresses for software polling. Otherwise, the flash memory returns a fixed reset vector instead of the hardware sequence flag value.
s Reset vector address in flash memory The following table shows the reset vector and mode data values determined in advance. Reset vector Mode data FFA000H 00H
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24.10 Example of Programming 2M/3M-Bit Flash Memory
24.10 Example of Programming 2M/3M-Bit Flash Memory
This section presents a programming example of 2M/3M-bit flash memory.
s Programming example of 2M/3M-bit flash memory Flash Memory Sample Program
NAME FLASHWE TITLE FLASHWE ;------------------------------------------------------------------------------;2M/3M-bit-FLASH test program ; ;1: Transmits the program (address: FFBC00H, sector: SA6) from FLASH to RAM ; (address: 001500H). ;2: Executes the program on RAM. ;3: Writes the PDR1 value to FLASH (address: FI0000H, sector: SA1). ;4: Reads the written value (address: FD0000H, sector: SA1) and outputs it to PDR2. ;5: Erases the written sector (SA1). ;6: Checks and outputs erase data. ;Conditions ; - Number of bytes transmitted to RAM: 100H (256B) ; - Write/erase termination judgment ; Judgment according to DQ5 (timing limit excess flag) ; Judgment according to DQ6 (toggle bit flag) ; Judgment according to RDY (FMCS) ; - Error handling ; Hi output to P00 to P07 ; Reset command issuance ;------------------------------------------------------------------; RESOUS IOSEG ABS=00 ;"RESOUS" I/O segment definition ORG 0000H PDR0 RB 1 PDR1 RB 1 PDR2 RB 1 PDR3 RB 1 ORG 0010H DDR0 RB 1 DDR1 RB 1 DDR2 RB 1 DDR3 RB 1 ORG 00A1H CKSCR RB 1 ORG 00AEH FMCS RB 1 ORG 006FH ROMM RB 1 RESOUS ENDS ; SSTA SSEG RW 0127H STA_T RW 1 SSTA ENDS ; DATA DSEG ABS=0FFH ;FLASH command address ORG 5554H COMADR2 RW 1 ORG 0AAAAH COMADR1 RW 1 DATA ENDS ;/////////////////////////////////////////////////////////////
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CHAPTER 24 2M/3M-BIT FLASH MEMORY
;Main program (FFA000H) ;///////////////////////////////////////////////////////////// CODE CSEG START: ; ///////////////////////////////////////////////////// ; Initialization ; ///////////////////////////////////////////////////// MOV CKSCR,#0BAH ;3-multiple setting MOV RP,#0 MOV A,#!STA_T MOV SSB,A MOVW A,#STA_T MOVW SP,A MOV ROMM,#00H ;Mirror OFF MOV PDR0,#00H ;For error check MOV DDR0,#0FFH MOV PDR1,#00H ;Port for data input MOV DDR1,#00H MOV PDR2,#00H ;Port for data output MOV DDR2,#0FFH ; ////////////////////////////////////////////////////////////// ; Transfer of "FLASH write erase program (FFBC00H)" to RAM (1500H address) ; ////////////////////////////////////////////////////////////// MOVW A,#1500H ;Transfer destination RAM area MOVW A,#0BC00H ;Transfer source address (program position) MOVW RW0,#100H ;Number of bytes to be transferred MOVS ADB,PCB ;Transfer of 100H from FFBC00H to 001500H CALLP 001500H ;Jump to the address containing the transferred ; program ; ///////////////////////////////////////////////////// ; Data output ; ///////////////////////////////////////////////////// OUT MOV A,#0FDH MOV ADB,A MOVW RW2,#0000H MOVW A,@RW2+00 MOV PDR2,A END JMP * CODE ENDS ;//////////////////////////////////////////////////////////// ;FLASH write erase program (SA6) ;//////////////////////////////////////////////////////////// RAMPRG CSEG ABS=0FFH ORG 0BC00H ; //////////////////////////////////////////// Initialization ; //////////////////////////////////////////// MOVW RW0,#0500H ;RW0:RAM space for input data acquisition 00:0500~ MOVW RW2,#0000H ;RW2:Flash memory write address FD:0000~ MOV A,#00H ;DTB modification MOV DTB,A ;Bank specification for @RW0 MOV A,#0FDH ;ADB modification 1 MOV ADB,A ;Bank specification for write mode specification ; address MOV PDR3,#00H ;Switch initialization MOV DDR3,#00H ; WAIT1 BBC PDR3:0,WAIT1 ;PDR3: 0(write start at high level) ; ;//////////////////////////////////////////////// ;Write (SA1) ;//////////////////////////////////////////////// MOV A,PDR1 MOVW @RW0+00,A ;PDR1 data allocation to RAM MOV FMCS,#20H ;Write mode setting MOVW ADB:COMADR1,#00AAH ;Flash write command 1 MOVW ADB:COMADR2,#0055H ;Flash write command 2 MOVW ADB:COMADR1,#00A0H ;Flash write command 3
378
24.10 Example of Programming 2M/3M-Bit Flash Memory
; MOVW A,@RW0+00 ;Input data (RW0) write to flash memory (RW2) MOVW @RW2+00,A ;Wait time check /////////////////////////////////////////////////////////////////// ERROR when the time limit excess check flag is set and toggle operation is in progress /////////////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOW ;Time limit over MOVW A,@RW2+00 ;AH MOVW A,@RW2+00 ;AL XORW A ;XOR of AH and AL (1 when the values differ) AND A,#40H ;Is the DQ6 toggle bit different? BNZ ERROR ;To ERROR when the DQ6 toggle bit is different /////////////////////////////////////// Write termination check (FMCS-RDY) /////////////////////////////////////// /////////////////////////////////////// MOVW A,FMCS AND A,#10H ;Extraction of FMCS RDY bit (bit 4) BZ WRITE ;End of write? MOV FMCS,#00H ;Write mode release ///////////////////////////////////////////////////// Write data output ///////////////////////////////////////////////////// MOVW RW2,#0000H ;Write data output MOVW A,@RW2+00 MOV PDR2,A
WRITE ; ; ; ;
; ; ; ; NTOW
; ; ;
; WAIT2 BBC PDR3:1,WAIT2 ;PDR3: 1(sector erase start at high level) ; ;///////////////////////////////////////////// ;Sector erase (SA1) ;///////////////////////////////////////////// MOV @RW2+00,#0000H ;Address initialization MOV FMCS,#20H ;Erase mode setting MOVW ADB:COMADR1,#00AAH ;Flash erase command 1 MOVW ADB:COMADR2,#0055H ;Flash erase command 2 MOVW ADB:COMADR1,#0080H ;Flash erase command 3 MOVW ADB:COMADR1,#00AAH ;Flash erase command 4 MOVW ADB:COMADR2,#0055H ;Flash erase command 5 MOV @RW2+00,#0030H ;Issuance of erase command 6 to the sector to be erased ELS ;Wait time check ; /////////////////////////////////////////////////////////////////// ; ERROR when the time limit excess check flag is set and toggle operation is ; in progress ; /////////////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOE ;Time limit over MOVW A,@RW2+00 ;AH High and Low are alternately output from MOVW A,@RW2+00 ;AL DQ6 per read during write operation. XORW A ;XOR of AH and AL (If the DQ6 value differs, ; write operation is in progress (1)). AND A,#40H ;Is the DQ6 toggle bit High? BNZ ERROR ;ERROR when the DQ6 toggle bit is High ; /////////////////////////////////////// ; Erase termination check (FMCS-RDY) ; /////////////////////////////////////// NTOE MOVW A,FMCS ; AND A,#10H ;Extraction of FMCS RDY bit (bit 4) BZ ELS ;End of sector erase? MOV FMCS,#00H ;FLASH erase mode release RETP ;Return to the main program ;//////////////////////////////////////////////
379
CHAPTER 24 2M/3M-BIT FLASH MEMORY
;Error ;////////////////////////////////////////////// ERROR MOV FMCS,#00H ;FLASH mode release MOV PDR0,#0FFH ;Error handling check MOV ADB:COMADR1,#0F0H ;Reset command (read is enabled) RETP ;Return to the main program RAMPRG ENDS ;///////////////////////////////////////////// VECT CSEG ABS=0FFH ORG 0FFDCH DSL START DB 00H VECT ENDS ;
380
CHAPTER 25
EXAMPLES OF F2MC-16LX MB90F591/ MB90F594A SERIAL WRITE CONNECTION
This chapter provides examples of F2MC-16LX MB90F591/MB90F594A serial write connection. 25.1 Basic Configuration of F2MC-16LX MB90F591/MB90F594A Serial Write Connection 25.2 Example of Serial Write Connection (User Power Supply Used) 25.3 Example of Serial Write Connection (Power Supplied from the Writer) 25.4 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used) 25.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Writer)
381
CHAPTER 25 EXAMPLES OF F2MC-16LX MB90F591/MB90F594A SERIAL WRITE CONNECTION
25.1 Basic Configuration of F2MC-16LX MB90F591/MB90F594A Serial Write Connection
The MB90F591/MB90F594A supports flash ROM serial onboard writing (Fujitsu standard). This section describes the specifications.
s Basic Configuration of F2MC-16LX MB90F591/MB90F594A Serial Write Connection The AF200 flash microcomputer programmer from Yokogawa Digital Computer Ltd. is used for Fujitsu standard serial onboard writing.
Host interface cable (AZ201)
General-purpose common cable (AZ210)
MB90F594A user system
AF200 flash microcomputer CLK synchronous serial programmer + memory card
Stand-alone operation enabled
Note: Ask the company representative from Yokogawa Digital Computer Ltd. for details about the functions and operations of the AF200 flash microcomputer programmer, general-purpose common cable for connection (AZ210), and connectors. Table 25.1-1 Pins Used for Fujitsu Standard Serial Onboard Writing Pin MD2, MD1 MD0 X0, X1 Function Mode pins Oscillation pins Additional information Controls write mode from the flash microcomputer programmer. In write mode, the CPU internal operation clock signal is one multiple of the PLL clock signal frequency. Therefore, because the oscillation clock frequency becomes the internal operation clock signal, the resonator used for serial rewriting is 1 MHz to 16 MHz. -
P00, P01 RSTX SIN3 SOT3 SCK3
Write program activation pins Reset pin Serial data input pin Serial data output pin Serial clock signal input pin Serial input-output is used.
382
25.1 Basic Configuration of F2MC-16LX MB90F591/MB90F594A Serial Write Connection Table 25.1-1 Pins Used for Fujitsu Standard Serial Onboard Writing (Continued) Pin C C pin Function Additional information This external capacitor pin is used to stabilize the power supply. Connect a ceramic capacitor of approximately 0.1F to the outside. If the write voltage (5 V10%) is supplied from the user system, the flash microcomputer programmer need not be connected. Connect so that the power supply of the user side is not short-circuited. Common to the ground of the flash microcomputer programmer. Input high level during serial write mode.
VCC
Supply voltage pin
VSS HSTX
GND pin Hardware standby pin
Even if the P00, SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial writing. Sections 25.2 to 25.5 present examples the following four types of serial write connection. See each Section as required. * * * * Serial write connection (user power supply used) Serial write connection (power supplied from the writer) Minimum connection to the flash microcomputer programmer (user power supply used) Minimum connection to the flash microcomputer programmer (power supplied from the writer)
AF200 write control pin 10K AF200 /TICS pin
MB90F594A / MB90F591 write control pin
User
Table 25.1-2 AF200 Flash Microcomputer Programmer System Configuration (Manufactured by Yokogawa Digital Computer Ltd.) Model AF200/ACP AF200/AC2P AZ201 AZ210 FF001 Function Flash microcomputer programmer and 100 V power adapter Flash microcomputer programmer and power adapter complying with overseas specifications PC/AT RS232C cable Standard target probe (a) length: 1 m Fujitsu F2MC-16LX flash microcomputer control module 383
CHAPTER 25 EXAMPLES OF F2MC-16LX MB90F591/MB90F594A SERIAL WRITE CONNECTION Table 25.1-2 AF200 Flash Microcomputer Programmer System Configuration (Manufactured by Yokogawa Digital Computer Ltd.) (Continued) Model FF001/P2 FF001/P4 2MB PC Card (Option) 4MB PC Card (Option) Function
Inquiries: Yokogawa Digital Computer Ltd., Sales Department of Machinery Business Center Telephone number: 042-333-6224
384
25.2 Example of Serial Write Connection (User Power Supply Used)
25.2 Example of Serial Write Connection (User Power Supply Used)
Figure 25.2-1 is an example of a serial write connection for internal vector modes (single-chip mode and internal ROM external bus mode) when the user power supply is used. The mode pins MD2, MD1, and MD0 are set to 011.
s Example of Serial Write Connection (User Power Supply Used)
Figure 25.2-1 Example of Serial Write Connection for MB90F591/MB90F594A Internal Vector Modes (User Power Supply Used)
User system AF200 flash microcomputer Connector DX10-28S or DX20-28S programmer
MB90F594A / MB90F591 MD2 MD1
TAUX3
(19)
TMODE
(12) 1MHz to 16MHz
MD0 X0 X1
TAUX /TICS
(23)
P00
(10)
User User
HSTX RSTX
User
/TRES
(5)
P01 C
SIN3 SOT3 SCK3
TTXD TRXD TCK TVcc
(13) (27) (6) (2)
(7,8, 14,15. 21,22 1,28)
Vcc
User power supply
GND
Vss
Pin 14 Pin 1
Pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25, and 26 are open. DX10-28S: Right-angle type DX20-28S: Straight type
DX10-28S DX20-28S Pin 28 Pin 15 Connector (Hirose Electronics Ltd.) pin arrangement
*
Even if the SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit 385
CHAPTER 25 EXAMPLES OF F2MC-16LX MB90F591/MB90F594A SERIAL WRITE CONNECTION shown in the figure below is required in the same way that it is for P00. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial writing. * Connect the AF200 while the user power is off.
AF200 write control pin 10K AF200 /TICS pin
MB90F594A / MB90F591 write control pin
User
386
25.3 Example of Serial Write Connection (Power Supplied from the Writer)
25.3 Example of Serial Write Connection (Power Supplied from the Writer)
Figure 25.3-1 is an example of a serial write connection for internal vector modes (single-chip mode and internal ROM external bus mode) when power is supplied from the writer. The mode pins MD2, MD1, and MD0 are set to 011.
s Example of Serial Write Connection (Power Supplied from the Writer)
Figure 25.3-1 Example of Serial Write Connection for MB90F591/MB90F594A Internal Vector Modes (Power Supplied from the Writer)
User system AF200 flash microcomputer Connector programmer DX10-28S or DX20-28S
TAUX3
(19)
MB90F594A / MB90F591 MD2 MD1
TMODE
(12) 1MHz to 16MHz
MD0 X0 X1
TAUX /TICS
(23)
P00
(10)
User User
HSTX RSTX
User
/TRES
(5)
P01 C
SIN3 SOT3 SCK3
TTXD TRXD TCK TVcc Vcc TVPP1
(13) (27) (6) (2) (3) (16)
(7,8, 14,15. 21,22 1,28)
Vcc
User power supply
GND
Vss
Pin 14 Pin 1
Pins 4, 9, 11, 17, 18, 20, 24, 25, and 26 are open. DX10-28S: Right-angle type DX20-28S: Straight type
DX10-28S DX20-28S
Pin 28 Pin 15 Connector (Hirose Electronics Ltd.) pin arrangement
*
Even if the SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit 387
CHAPTER 25 EXAMPLES OF F2MC-16LX MB90F591/MB90F594A SERIAL WRITE CONNECTION shown in the figure below is required in the same way that it is for P00. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial writing. * * Connect the AF200 while the user power is off. When the write power is supplied from the AF200, be careful not to short-circuit the user power supply.
AF200 write control pin 10K AF200 /TICS pin
MB90F594A / MB90F591 write control pin
User
388
25.4 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply
25.4 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used)
Figure 25.4-1 is an example of the minimum connection to the flash microcomputer programmer when the user power supply is used.
s Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used) For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputer programmer need not be connected if the pins are set as described below. Figure 25.4-1 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used)
AF200 User system flash microcomputer programmer 1 for serial rewrite
1 for serial rewrite MB90F594A MB90F591
MD2 MD1 MD0
0 for serial rewrite
X0
1MHz to 16MHz
X1 P00
0 for serial rewrite User circuit 1 for serial rewrite User circuit
Connector DX10-28S or DX20-28S
P01 HSTX C RSTX
SIN3 SOT3 SCK3
/TRES TTXD TRXD TCK TVcc
(5) (13) (27) (6) (2)
(7,8, 14,15, 21,22, 1,28)
Vcc
User power supply
GND
Vss
Pin 14 Pin 1
Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19, 20, 23, 24, 25, and 26 are open. DX10-28S: Right-angle type DX20-28S: Straight type
DX10-28S DX20-28S
Pin 28 Pin 15 Connector (Hirose Electronics Ltd.) pin arrangement
*
Even if the SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit shown in the figure below is required. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial writing. 389
CHAPTER 25 EXAMPLES OF F2MC-16LX MB90F591/MB90F594A SERIAL WRITE CONNECTION * Connect the AF200 while the user power is off.
AF200 write control pin 10K AF200 /TICS pin
MB90F594A / MB90F591 write control pin
User
390
25.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the
25.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Writer)
Figure 25.5-1 is an example of the minimum connection to the flash microcomputer programmer when power is supplied from the writer.
s Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Writer) For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputer programmer need not be connected if the pins are set as described below. Figure 25.5-1 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Writer)
AF200 flash microcomputer programmer User system
1 for serial rewrite MB90F594A/ MB90F591
MD2
1 for serial rewrite
MD1 MD0
0 for serial rewrite
X0
1MHz to 16MHz
X1 P00
0 for serial rewrite User circuit 1 for serial rewrite User circuit
Connector DX10-28S or DX20-28S
P01 HSTX C RSTX
SIN3 SOT3 SCK3
/TRES TTXD TRXD TCK TVcc
(5) (13) (27) (6) (2) (3) (16) (7,8, 14,15, 21,22, 1,28)
Vcc Vss
Pin 14 Pin 1
GND
Pins 4, 9, 10, 11, 12, 17, 18, 19, 20, 23, 24, 25, and 26 are open. DX10-28S: Right-angle type DX20-28S: Straight type
DX10-28S DX20-28S
Pin 28 Pin 15 Connector (Hirose Electronics Ltd.) pin arrangement
*
Even if the SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit 391
CHAPTER 25 EXAMPLES OF F2MC-16LX MB90F591/MB90F594A SERIAL WRITE CONNECTION shown in the figure below is required. The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial writing. * * Connect the AF200 while the user power is off. When the write power is supplied from the AF200, be careful not to short-circuit the user power supply.
AF200 write control pin 10K AF200 /TICS pin
MB90F594A / MB90F591 write control pin
User
392
APPENDIX
The appendixes provide I/O maps, instructions, and other information. A I/O Maps B Instructions C Timing Diagram in Flash Memory Mode D List of MB90590 Interrupt Vectors
393
APPENDIX A I/O Maps
APPENDIX A I/O Maps
Table A-1 lists addresses to be assigned to the registers in the peripheral blocks.
s I/O Maps
Table A-1 I/O Map Address 00 H 01 H 02 H 03 H 04 H 05 H 06 H 07 H 08 H 09 H 0A to 0FH 10 H 11 H 12 H 13 H 14 H 15 H 16 H 17 H 18 H 19 H 1A H 1B H 1C to 1F H Analog input enable Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Abbrevia -tion PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Peripheral Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ---XXXXX XXXXXXXX XXXXXXXX
Use prohibited DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 --000000
Use prohibited ADER R/W Port 6, A/D 11111111
Use prohibited
394
APPENDIX A I/O Maps Table A-1 I/O Map (Continued) Address 20 H 21 H 22 H 23 H 24 H 25 H 26 H 27 H 28 H 29 H 2A H 2B H 2C H 2D H 2E H 2F H 30 H 31 H 32 H 33 H 34 H 35 H 36 H 37 H 38 H 39 H 3A H 3B H Register Serial mode control 0 Status 0 Input/output data 0 Rate/data 0 Serial mode control 1 Status 1 Input/output data 1 Rate/data 1 Serial mode control 2 Status 2 Input/output data 2 Rate/data 2 Serial mode control Serial mode control Serial data Edge selector External interrupt enable External interrupt request External interrupt level External interrupt level A/D control status 0 A/D control status 1 A/D data 0 A/D data 1 PPG0 operation mode control register PPG1 operation mode control register PPG0/PPG1 clock select register Abbrevia -tion UMC0 USR0 UIDR0/ UODR0 URD0 UMC1 USR1 UIDR1/ UODR1 URD1 UMC2 USR2 UIDR2/ UODR2 URD2 SMCS SMCS SDR SES ENIR EIRR ELVR ELVR ADCS0 ADCS1 ADCR0 ADCR1 PPGC0 PPGC1 PPC01 Access R/W R/W UART0 R/W R/W R/W R/W UART1 R/W R/W R/W R/W UART2 R/W R/W R/W R/W Serial I/O R/W R/W R/W R/W R/W R/W R/W R/W A/D converter R R/W R/W R/W R/W 16-bit programmable pulse generator 0/1 XXXXXXXX 000010XX 0-000--1 0-000001 00000000 External interrupt XXXXXXXX -------0 00000000 XXXXXXXX 00000000 00000000 00000000 00000000 XXXXXXXX 0000000X ----0000 00000010 XXXXXXXX 0000000X 00000100 00010000 XXXXXXXX 0000000X 00000100 00010000 Peripheral Initial value 00000100 00010000
Use prohibited
395
APPENDIX A I/O Maps Table A-1 I/O Map (Continued) Address 3C H 3D H 3E H 3F H 40 H 41 H 42 H 43 H 44 H 45 H 46 H 47 H 48 H 49 H 4A H 4B H 4C H 4D H 4E H 4F H 50 H 51 H 52 H 53 H Timer control status 0 Timer control status 0 Timer control status 1 Timer control status 1 PPGA operation mode control register PPGB operation mode control register PPGA/PPGB clock select register PPG8 operation mode control register PPG9 operation mode control register PPG8/PPG9 clock select register PPG6 operation mode control register PPG7 operation mode control register PPG6/PPG7 clock select register PPG4 operation mode control register PPG5 operation mode control register PPG4/PPG5 clock select register Register PPG2 operation mode control register PPG3 operation mode control register PPG2/PPG3 clock select register Abbrevia -tion PPGC2 PPGC3 PPG23 Access R/W R/W R/W Peripheral Initial value 0-000--1 0-000001 00000000
16-bit programmable pulse generator 2/3
Use prohibited PPGC4 PPGC5 PPG45 R/W R/W R/W 16-bit programmable pulse generator 4/5 0-000--1 0-000001 00000000
Use prohibited PPGC6 PPGC7 PPG67 R/W R/W R/W 16-bit programmable pulse generator 6/7 0-000--1 0-000001 00000000
Use prohibited PPGC8 PPGC9 PPG89 R/W R/W R/W 16-bit programmable pulse generator 8/9 0-000--1 0-000001 00000000
Use prohibited PPGCA PPGCB PPGAB R/W R/W R/W 16-bit programmable pulse generator A/B 0-000--1 0-000001 00000000
Use prohibited TMCSR0 TMCSR0 TMCSR1 TMCSR1 R/W R/W R/W R/W 16-bit reload timer 0 16-bit reload timer 1 00000000 ----0000 00000000 ----0000
396
APPENDIX A I/O Maps Table A-1 I/O Map (Continued) Address 54 H 55 H 56 H 57 H 58 H 59 H 5A H 5B H 5C H 5D H 5E H 5F H 60 H 61 H 62 H 63 H 64 H 65 H 66 H 67 H 68 H 69 H 6A to 6C H 6D H Serial I/O prescaler PWM control 3 PWM control 2 PWM control 1 Output compare control status 0 Output compare control status 1 Output compare control status 2 Output compare control status 3 Output compare control status 4 Output compare control status 5 Sound control Sound control Watch-dog timer control Watch-dog timer control PWM control 0 Register Input capture control status 0/1 Input capture control status 2/3 Input capture control status 4/5 Abbrevia -tion ICS01 ICS23 ICS45 Access R/W R/W R/W Peripheral Input capture 0/1 Input capture 2/3 Input capture 4/5 Initial value 00000000 00000000 00000000
Use prohibited OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 SGCR SGCR WTCR WTCR PWC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare 0/1 Output compare 2/3 Output compare 4/5 Sound generator Watch-dog timer Stepping motor controller 0 0000--00 ---00000 0000--00 ---00000 0000--00 ---00000 00000000 0------0 000--000 00000000 00000--0
Use prohibited PWC1 R/W Stepping motor controller 1 00000--0
Use prohibited PWC2 R/W Stepping motor controller 2 00000--0
Use prohibited PWC3 R/W Stepping motor controller 3 00000--0
Use prohibited Use prohibited CDCR R/W Prescaler (Serial I/O) 0XXX1111
397
APPENDIX A I/O Maps Table A-1 I/O Map (Continued) Address 6E H 6F H 70 to 8F H 90 to 9D H 9E H 9F H A0 H A1 H A2 to A7H A8 H A9 H AA to AD H AE H AF H Flash control status (only for MB90F594. Use prohibited for other controllers.) Watch-dog control Time base timer control register ROM correction control status Delayed interrupt/release Low-power mode Clock selection Register Timer control ROM mirror Abbrevia -tion TCCS ROMM Access R/W W Peripheral I/O timer ROM mirror Initial value 00000000 XXXXXXX1
Reserved for CAN interface 0/1. See the "CAN Controller Hardware Manual." Use prohibited PACSR DIRR LPMCR CKSCR R/W R/W R/W R/W ROM correction Delayed interrupt Low-power control circuit 00000000 -------0 00011000 11111100
Use prohibited WDTC TBTC R/W R/W Watch-dog timer Time base timer XXXXX111 1--00100
Use prohibited FMCS R/W Flash memory 000X0--0
Use prohibited
398
APPENDIX A I/O Maps Table A-1 I/O Map (Continued) Address B0 H B1 H B2 H B3 H B4 H B5 H B6 H B7 H B8 H B9 H BA H BB H BC H BD H BE H BF H C0 to FF H Register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Abbrevia -tion ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller Peripheral Initial value 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111
Use prohibited
Table A-2 I/O Map (19XX Address) Address 1900 H 1901 H 1902 H 1903 H 1904 H 1905 H 1906 H 1907 H Register Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Abbreviation PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 Access R/W R/W R/W R/W R/W R/W R/W R/W 16-bit programmable pulse generator 2/3 16-bit programmable pulse generator 0/1 Peripheral Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
399
APPENDIX A I/O Maps Table A-2 I/O Map (19XX Address) (Continued) Address 1908 H 1909 H 190A H 190B H 190C H 190D H 190E H 190F H 1910 H 1911 H 1912 H 1913 H 1914 H 1915 H 1916 H 1917 H 1918 to 191F H 1920 H 1921 H 1922 H 1923 H 1924 H 1925 H 1926 H 1927 H 1928 H 1929 H 192A H 192B H 192D to 192F H Input capture 0 Input capture 0 Input capture 1 Input capture 1 Input capture 2 Input capture 2 Input capture 3 Input capture 3 Input capture 4 Input capture 4 Input capture 5 Input capture 5 IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3 IPCP4 IPCP4 IPCP5 IPCP5 Register Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Abbreviation PRLL4 PRLH4 PRLL5 PRLH5 PRLL6 PRLH6 PRLL7 PRLH7 PRLL8 PRLH8 PRLL9 PRLH9 PRLLA PRLHA PRLLB PRLHB Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Use prohibited R R Input capture 0/1 R R R R Input capture 2/3 R R R R R R Use prohibited Input capture 4/5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit programmable pulse generator A/ B 16-bit programmable pulse generator 8/9 16-bit programmable pulse generator 6/7 16-bit programmable pulse generator 4/5 Peripheral Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
400
APPENDIX A I/O Maps Table A-2 I/O Map (19XX Address) (Continued) Address 1930 H 1931 H 1932 H 1933 H 1934 H 1935 H 1936 H 1937 H 1938 H 1939 H 193A H 193B H 193D to 193F H 1940 H 1941 H 1942 H 1943 H 1944 H 1945 H 1946 H 1947 H 1948 H 1949 H Timer 0/reload 0 Timer 0/reload 0 Timer 1/reload 1 Timer 1/reload 1 Timer data Timer data Frequency data Amplitude data Decrement grade Tone count Register Output compare 0 Output compare 0 Output compare 1 Output compare 1 Output compare 2 Output compare 2 Output compare 3 Output compare 3 Output compare 4 Output compare 4 Output compare 5 Output compare 5 Abbreviation OCCP0 OCCP0 OCCP1 OCCP1 OCCP2 OCCP2 OCCP3 OCCP3 OCCP4 OCCP4 OCCP5 OCCP5 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Use prohibited TMR0/ TMRLR0 TMR0/ TMRLR0 TMR1/ TMRLR1 TMR1/ TMRLR1 TCDT TCDT SGFR SGAR SGDR SGTR R/W 16-bit reload timer 0 R/W R/W 16-bit reload timer 1 R/W R/W I/O timer R/W R/W R/W Sound generator R/W R/W XXXXXXXX XXXXXXXX 00000000 XXXXXXXX XXXXXXXX XXXXXXXX 00000000 XXXXXXXX XXXXXXXX XXXXXXXX Output compare 4/ 5 Output compare 2/ 3 Output compare 0/ 1 Peripheral Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
401
APPENDIX A I/O Maps Table A-2 I/O Map (19XX Address) (Continued) Address 194A H 194B H 194C H 194D H 194E H 194F H 1950 H 1951 H 1952 H 1953 H 1954 H 1955 H 1956 H 1957 H 1958 H 1959 H 195A H 195B H 195C H 195D H 195E H 195F H 1960 to 19FF H 1A00 to 1AFF H 1B00 to 1BFF H 1C00 to 1CFF H 1D00 to 1DFF H 1E00 to 1EFF H 402 Register Subsecond data Subsecond data Subsecond data Second data Minute data Hour data PWM1 compare 0 PWM2 compare 0 PWM1 select 0 PWM2 select 0 PWM1 compare 1 PWM2 compare 1 PWM1 select 1 PWM2 select 1 PWM1 compare 2 PWM2 compare 2 PWM1 select 2 PWM2 select 2 PWM1 compare 3 PWM2 compare 3 PWM1 select 3 PWM2 select 3 Abbreviation WTBR WTBR WTBR WTSR WTMR WTHR PWC10 PWC20 PWS10 PWS20 PWC11 PWC21 PWS11 PWS21 PWC12 PWC22 PWS12 PWS22 PWC13 PWC23 PWS13 PWS23 Access R/W R/W R/W Watchdog timer R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Stepping motor controller 3 Stepping motor controller 2 Stepping motor controller 1 Stepping motor controller 0 --000000 --000000 ---00000 XXXXXXXX XXXXXXXX --000000 -0000000 XXXXXXXX XXXXXXXX --000000 -0000000 XXXXXXXX XXXXXXXX --000000 -0000000 XXXXXXXX XXXXXXXX --000000 -0000000 Peripheral Initial value XXXXXXXX XXXXXXXX ---XXXXX
Used prohibited Reserved for CAN interface 0. See the "CAN Controller Hardware Manual." Reserved for CAN interface 1. See the "CAN Controller Hardware Manual." Reserved for CAN interface 0. See the "CAN Controller Hardware Manual." Reserved for CAN interface 1. See the "CAN Controller Hardware Manual." Use prohibited
APPENDIX A I/O Maps Table A-2 I/O Map (19XX Address) (Continued) Address 1EF0 H 1EF1 H 1EF2 H 1EF3 H 1EF4 H 1EF5 H 1EF6 to 1FFF H * * Register ROM correction address 0 ROM correction address 1 ROM correction address 2 ROM correction address 3 ROM correction address 4 ROM correction address 5 Abbreviation PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 Access R/W R/W R/W ROM correction R/W R/W R/W Use prohibited Initial value "?" indicates an unused bit, and "X" indicates an undefined value. The addresses between 0000H and 00FFH, which are not listed, have been reserved for the main functions of the MCU. The result of read access to these reserved addresses is "X." Write access to these addresses is not allowed. XXXXXXXX XXXXXXXX XXXXXXXX Peripheral Initial value XXXXXXXX XXXXXXXX XXXXXXXX
r Explanation of write and read R/W: Both read and write enabled R: Only read enabled W: Only write enabled r Explanation of initial values 0: The initial value of this bit is "0". 1: The initial value of this bit is "1". X: The initial value of this bit is undefined. -: This bit is not used, and the initial value is undefined.
403
APPENDIX B INSTRUCTIONS
APPENDIX B INSTRUCTIONS
Appendix B describes the instructions used by the F2MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Number of Execution Cycles B.6 Effective Address Field B.7 How to Read the Instruction List B.8 F2MC-16LX Instruction List B.9 Instruction Map
404
APPENDIX B INSTRUCTIONS
B.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself.
s Instruction Types The F2MC-16LX supports the following 351 types of instructions: * * * * * * * * * * * * * * * * * 41 transfer instructions (byte) 38 transfer instructions (word or long word) 42 addition/subtraction instructions (byte, word, or long word) 12 increment/decrement instructions (byte, word, or long word) 11 comparison instructions (byte, word, or long word) 11 unsigned multiplication/division instructions (word or long word) 11 signed multiplication/division instructions (word or long word) 39 logic instructions (byte or word) 6 logic instructions (long word) 6 sign inversion instructions (byte or word) 1 normalization instruction (long word) 18 shift instructions (byte, word, or long word) 50 branch instructions 6 accumulator operation instructions (byte or word) 28 other control instructions (byte, word, or long word) 21 bit operation instructions 10 string instructions
405
APPENDIX B INSTRUCTIONS
B.2
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used. Some instructions permit the user to select several types of addressing.
s Addressing The F2MC-16LX supports the following 23 types of addressing: * * * * * * * * * * * * * * * * * * * * * * * Immediate (#imm) Register direct Direct branch address (addr16) Physical direct branch address (addr24) I/O direct (io) Abbreviated direct address (dir) Direct address (addr16) I/O direct bit address (io:bp) Abbreviated direct bit address (dir:bp) Direct bit address (addr16:bp) Vector address (#vct) Register indirect (@RWj j = 0 to 3) Register indirect with post increment (@RWj+ j = 0 to 3) Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj+ disp16 j = 0 to 3) Long register indirect with displacement (@RLi + disp8 i = 0 to 3) Program counter indirect with displacement (@PC + disp16) Register indirect with base index (@RW0 + RW7, @RW1 + RW7) Program counter relative branch address (rel) Register list (rlst) Accumulator indirect (@A) Accumulator indirect branch address (@A) Indirectly-specified branch address (@ear) Indirectly-specified branch address (@eam)
406
APPENDIX B INSTRUCTIONS s Effective Address Field Table B.1 lists the address formats specified by the effective address field. Table B.2-1 Effective Address Field Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 @RW0 @RW1 @RW2 @RW3 @RW0+ @RW1+ @RW2+ @RW3+ @RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8 @RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16 @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 Representation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Address format Default bank
Register direct: Individual parts correspond to the byte, word, and long word types in order from the left.
None
Register indirect
DTB DTB ADB SPB DTB DTB ADB SPB DTB DTB ADB SPB DTB DTB ADB SPB DTB DTB ADB SPB DTB DTB PCB DTB
Register indirect with post increment
Register indirect with 8-bit displacement
Register indirect with 8-bit displacement
Register indirect with 16-bit displacement Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
407
APPENDIX B INSTRUCTIONS
B.3
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing mode.
s Direct Addressing
r Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of immediate addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.) Before execution After execution A A 2233 4455 4 4 5 5 1 2 1 2 (Some instructions transfer AL to AH.)
r Register direct addressing Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.3-2 shows an example of register direct addressing. Table B.3-1 Direct Addressing Registers General-purpose register Byte Word Long word Special-purpose register Accumulator Pointer Bank Page Control R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, R5W, RW6, RW7 RL0, RL1, RL2, RL3 A, AL SP* PCB, DTB, USB, SSB, ADB DPR PS, CCR, RP, ILM
*1 One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on the value of the S flag bit in the condition code register (CCR). For branch instructions, the program counter (PC) is not specified in an instruction operand but is specified
408
APPENDIX B INSTRUCTIONS implicitly. Figure B.3-2 Example of Register Direct Addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the general-purpose register R0.) Before execution After execution A A 0716 2534 0716 2564
Memory address space
R0
??
Memory address space
R0
34
r Direct branch addressing (addr16) Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which indicates the branch destination in the logical address space. Direct branch addressing is used for an unconditional branch, subroutine call, or software interrupt instruction. Bits 23 to 16 of the address are specified by the program bank register (PCB). Figure B.3-3 Example of Direct Branch Addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch addressing in a bank.) Before execution PC 3 C 2 0 PCB 4 F
Memory address space
4F3C22H 4F3C21H 4F3C20H
3B 20 62
JMP 3B20H
After execution
PC 3 B 2 0
PCB 4 F
4F3B20H
Next instruction
r Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of Direct Branch Addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit addressing.) Before execution PC 3 C 2 0 PCB 4 F
Memory address space
4F3C23H 4F3C22H 4F3C21H 4F3C20H
33 3B 20 63
Next instruction
JMPP 333B20H
After execution
PC 3 B 2 0
PCB 3 3
333B20H
409
APPENDIX B INSTRUCTIONS r I/O direct addressing (io) Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB) and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an instruction using I/O direct addressing. Figure B.3-5 Example of I/O Direct Addressing (io)
MOVW A, i:0C0H (This instruction reads data by I/O direct addressing and stores it in A.) Before execution A 0716 2534
Memory address space
0000C1H 0000C0H After execution A 2534 FFEE
FF EE
r Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Figure B.3-6 Example of Abbreviated Direct Addressing (dir)
MOVW S;20H, A
(This instruction writes the contents of the eight low-order bits of A in abbreviated direct addressing mode.)
Before execution A
4455 66
1212
Memory address space
DTB 7 7 1212
776620H
??
After execution
A
4455 66
Memory address space
DTB 7 7
776620H
12
r Direct addressing (addr16) Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for this mode of addressing. Figure B.3-7 Example of Direct Addressing (addr16)
BRA 3B20H (This instruction causes an unconditional relative branch.) Before execution PC
3C20 PCB 4 F
Memory address space
4F3C22H 4F3C21H 4F3C20H FF FE 60
BRA 3B20H
After execution
PC
3B20
PCB 4 F 4F3B20H Next instruction
410
APPENDIX B INSTRUCTIONS r I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp)
SETB I:0C1H: (This instruction sets bits by I/O direct bit addressing.)
Memory address space
Before execution
0000C1H
00
After execution
0000C1H
01
r Abbreviated direct bit addressing (dir:bp) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)
SETB S:10H:0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory address space
Before execution DTB 5 5
DPR 6 6
556610H
00
Memory address space
After execution
DTB 5 5
DPR 6 6
556610H
01
r Direct bit addressing (addr16:bp) Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-10 Example of Direct Bit addressing (addr16:bp)
SETB 2222H:0 (This instruction sets bits by direct bit addressing.)
Memory address space
Before execution DTB 5 5
552222H
00
Memory address space
After execution
DTB 5 5
552222H
01
r Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two 411
APPENDIX B INSTRUCTIONS sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of Vector Addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.)
Before execution
PC
0000
Memory address space
FFFFE1H FFFFE0H D0 00
PCB F F
After execution
PC
D000 FFC000H EF CALLV #15
PCB F F
Table B.3-2 CALLV Vector List Instruction CALLV #0 CALLV #1 CALLV #2 CALLV #3 CALLV #4 CALLV #5 CALLV #6 CALLV #7 CALLV #8 CALLV #9 CALLV #10 CALLV #11 CALLV #12 CALLV #13 CALLV #14 CALLV #15 Vector address L XFFFEH XFFFCH XFFFAH XFFF8H XFFF6H XFFF4H XFFF2H XFFF0H XFFEEH XFFECH XFFEAH XFFE8H XFFE6H XFFE4H XFFE2H XFFE0H Vector address H XXFFFFH XXFFFDH XXFFFBH XXFFF9H XXFFF7H XXFFF5H XXFFF3H XXFFF1H XXFFEFH XXFFEDH XXFFEBH XXFFE9H XXFFE7H XXFFE5H XXFFE3H XXFFE1H
Note: A PCB register value is set in XX. Note: When the program bank register (PCB) is FFH, the vector area overlaps the vector area of INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3).
412
APPENDIX B INSTRUCTIONS
B.4
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of an operand.
s Indirect Addressing
r Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores it in A.)
Before execution
A
0716
2534
Memory address space
78D310H 78D30FH FF EE
RW1 D 3 0 F DTB 7 8
After execution
A
2534 FFEE
RW1 D 3 0 F DTB 7 8
r Register indirect addressing with post increment (@RWj+ j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. After operand operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word). Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. If the post increment results in the address of the register that specifies the increment, the incremented value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to writing by an instruction and, therefore, the register that would be incremented becomes write data. Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj + j = 0
413
APPENDIX B INSTRUCTIONS to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A
0716
2534
Memory address space
78D310H 78D30FH FF EE
RW1 D 3 0 F DTB 7 8
After execution
A
2534 FFEE
RW1 D 3 1 1 DTB 7 8
r Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) Memory is accessed using the address obtained by adding an offset to the contents of generalpurpose register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is used, or additional data bank register (ADB) when RW2 or RW6 is used. Figure B.4-3 Example of Register Indirect Addressing with Offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with an offset and stores it in A.)
Before execution
A
0716
2534
Memory address space
78D320H 78D31FH (+10H) FF EE
RW1 D 3 0 F DTB 7 8
After execution
A
2534 FFEE
RW1 D 3 0 F DTB 7 8
r Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value. Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an offset and stores it in A.)
Before execution A
RL2
0716
2534
Memory address space
824B28H 824B27H (+25H) FF EE
F382 4B02
After execution
A RL2
2534 FFEE F382 4B02
414
APPENDIX B INSTRUCTIONS r Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bits 16 to 23 are specified by the program bank register (PCB). Note that the operand address of each of the following instructions is not deemed to be (next instruction address + disp16): * * * DBNZ eam, rel DWBNZ eam, rel CBNE eam, #imm8, rel CWBNE eam, #imm16, rel MOV eam, #imm8 MOVW eam, #imm16 Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect addressing with a offset and stores it in A.)
Before execution
A
0716
2534
Memory address space
PCB C 5 PC 4 5 5 6
C5457BH C5457AH
FF EE
After execution
A
2534 FFEE
PCB C 5 PC 4 5 5 A
C5455AH +20H C54559H +4 C54558H C54557H C54556H
00 20 9E 73
MOVW A, @PC+20H
r Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of general-purpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB). Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a base index and stores it in A.)
Before execution
A
0716
2534 DTB 7 8 +
Memory address space
78D411H 78D410H FF EE
RW1 D 3 0 F RW7 0 1 0 1
After execution
A
2534 FFEE DTB 7 8
RW1 D 3 0 F RW7 0 1 0 1
r Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to 23 are indicated by the program bank
415
APPENDIX B INSTRUCTIONS register (PCB). Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel)
BRA 3B20H (This instruction causes an unconditional relative branch.)
Before execution PC
3C20
PCB 4 F
Memory address space
4F3C22H 4F3C21H 4F3C20H FF FE 60
BRA 3B20H
After execution
PC
3B20
PCB 4 F 4F3B20H
r Register list (rlst) Specify a register to be pushed onto or popped from a stack. Figure B.4-8 Configuration of the Register List
MSB LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
Figure B.4-9 Example of Register List (rlist)
POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple
word registers indicated by the register list.)
SP RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7
34FA
SP RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 34FEH 34FDH 34FCH 34FBH 34FAH SP
34FE 02 01
04 03
Memory address space
Memory address space
SP
04 03 02 01
04 03 02 01
34FEH 34FDH 34FCH 34FBH 34FAH
Before execution
After execution
416
APPENDIX B INSTRUCTIONS r Accumulator indirect addressing (@A) Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB). Figure B.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
Memory address space
BB2535H BB2534H FF EE
DTB B B
After execution
A
0716 FFEE
DTB B B
r Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program bank register (PCB). For the Jump Context (JCTX) instruction, however, address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for unconditional branch instructions. Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect branch addressing.)
Before execution PC
A
3C20 6677
PCB 4 F 3B20
Memory address space
4F3C20H 61 JMP @A
4F3B20H
Next instruction
After execution
PC A
3B20 6677
PCB 4 F 3B20
417
APPENDIX B INSTRUCTIONS r Indirect specification branch addressing (@ear) The address of the branch destination is the word data at the address indicated by ear. Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect addressing.)
Before execution
PC
3C20
PCB 4 F DTB 2 1
Memory address space
4F3C21H 4F3C20H 4F3B20H 08 73
PW0 7 F 4 8
JMP @@RW0
Next instruction
After execution
PC
3B20
PCB 4 F DTB 2 1
217F49H 217F48H
3B 20
PW0 7 F 4 8
r Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.)
Before execution PC
3C20
PCB 4 F
Memory address space
4F3C21H 4F3C20H 00 73
PW0 3 B 2 0
JMP @RW0
After execution
PC
3B20
PCB 4 F
4F3B20H
Next instruction
PW0 3 B 2 0
418
APPENDIX B INSTRUCTIONS
B.5 Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch.
s Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments. Therefore, intervening in data access increases the execution cycle count. Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the program fetches every byte of an instruction being executed. Therefore, intervening in data access increases the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register, internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register. Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add the "access count x cycle count for the halt" as a correction value to the normal execution count. s Calculating the Execution Cycle Count Table B.5-1 lists execution cycle counts and Tables B.5-2 and B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode (a)* Code Operand Execution cycle count in each addressing mode See the instruction list. Register access count in each addressing mode
00 | 07 08 | 0B 0C | 0F 10 | 17
Ri Rwi RLi @RWj
See the instruction list.
2
1
@RWj+
4
2
@RWi+disp8
2
1
419
APPENDIX B INSTRUCTIONS Table B.5-1 Execution Cycle Counts in Each Addressing Mode (Continued) (a)* Code Operand Execution cycle count in each addressing mode 2 4 4 2 1 Register access count in each addressing mode
18 | 1B 1C 1D 1E 1F
@RWi+disp16 @RW0+RW7 @RW1+RW7 @PC+disp16 addr16
1 2 2 0 0
*: (a) is used for ~ (cycle count) and B (correction value) in B-8, "F2MC-16LX Instruction List."
Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte*1 Operand Cycle count +0 +0 +0 +1 +1 +1 Access count 1 1 1 1 1 1 (c) word*1 Cycle count +0 +0 +2 +1 +4 +4 Access count 1 1 2 1 2 2 (d) long*1 Cycle count +0 +0 +4 +2 +8 +8 Access count 2 2 4 2 4 4
Internal register Internal memory Even address Internal memory Odd address External data bus 16-bit even address External data bus 16-bit odd address External data bus (*2) 28 bits
*1: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in B.8, "F2MC-16LX Instruction List." *2: When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles Instruction Internal memory External data bus 16 bits External data bus 8 bits Byte boundary -- -- +3 Word boundary +2 +3 --
420
APPENDIX B INSTRUCTIONS Notes: 1. When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. 2. Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the correction values to calculate the worst case.
421
APPENDIX B INSTRUCTIONS
B.6
Effective Address Field
Table B.6-1 shows the effective address field.
s Effective Address Field
Table B.6-1 Effective Address Field Byte count of extended address part (*1)
Code
Representation
Address format
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
R0 R1 R2 R3 R4 R5 R6 R7 @RW0 @RW1 @RW2 @RW3 @RW0+ @RW1+ @RW2+ @RW3+
RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7
RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3)
Register direct: Individual parts correspond to the byte, word, and long word types in order from the left.
--
Register indirect
0
Register indirect with post increment
0
@RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8 @RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16 @RW0+RW7 @RW1+RW7 @PC+disp16 addr16
Register indirect with 8-bit displacement
1
Register indirect with 16-bit displacement Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
2
0 0 2 2
*1 Each byte count of the extended address part applies to + in the # (byte count) column in the
422
APPENDIX B INSTRUCTIONS "F2MC-16LX Instruction List" in Appendix B.8.
423
APPENDIX B INSTRUCTIONS
B.7
How to Read the Instruction List
Table B.7-1describes the items used in the F2MC-16LX Instruction List, and Table B.7-2 describes the symbols used in the same list.
s Description of instruction presentation items and symbols
Table B.7-1 Description of Items in the Instruction List Item Mnemonic # ~ Description Uppercase, symbol: Represented as is in the assembler. Lowercase: Rewritten in the assembler. Number following lowercase: Indicates bit length in the instruction. Indicates the number of bytes. Indicates the number of cycles. See Table B.2a for the alphabetical letters in items. Indicates the number of times a register access is performed during instruction execution. The number is used to calculate the correction value for CPU intermittent operation. Indicates the correction value used to calculate the actual number of cycles during instruction execution. The actual number of cycles during instruction execution can be determined by adding the value in the ~ column to this value. Indicates the instruction operation. Indicates the special operation for bits 15 to 08 of the accumulator. Z: Transfers 0. X: Transfers after sign extension. -: No transfer Indicates the special operation for the 16 high-order bits of the accumulator. *: Transfers from AL to AH. -: No transfer Z: Transfers 00 to AH. X: Transfers 00H or FFH to AH after AL sign extension.
RG
B
Operation
LH
AH
424
APPENDIX B INSTRUCTIONS Table B.7-1 Description of Items in the Instruction List (Continued) Item I S T N Z V C Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory). *: Read Modify Write instruction -: Not Read Modify Write instruction Note: Cannot be used for an address that has different meanings between read and write operations. Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution. -: No change Z: Set upon instruction execution. X: Reset upon instruction execution. Description
RMW
Table B.7-2 Explanation on Symbols in the Instruction List Symbol A Explanation The bit length used varies depending on the 32-bit accumulator instruction. low-order bits of byte AL 16 bits of word AL long AL: 32 bits of AH 16 high-order bits of A 16 low-order bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7
AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri
425
APPENDIX B INSTRUCTIONS Table B.7-2 Explanation on Symbols in the Instruction List (Continued) Symbol RWi RWj RLi dir addr16 addr24 ad24 0-15 ad24 16-23 io #imm4 #imm8 #imm16 #imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b rel car eam rlst Explanation RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Abbreviated direct addressing Direct addressing Physical direct addressing Bits 0 to 15 of addr24 Bits 16 to 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data obtained by sign extension of 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address PC relative branch effective addressing (code 00 to 07) Effective addressing (code 08 to 1F) Register list
426
APPENDIX B INSTRUCTIONS
B.8
F2MC-16LX Instruction List
Tables B.8-1 to B.9-19 list the instructions used by the F2MC-16LX.
Table B.8-1 41 Transfer Instructions (byte)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH
A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RLi+disp8 A,#imm4 A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RWi+disp8 A,@RLi+disp8 dir,A addr16,A Ri,A ear,A eam,A io,A RLi+disp8,A Ri,ear Ri,eam ear,Ri eam,Ri Ri,#imm8 io,#imm8 dir,#imm8 ear,#imm8 eam,#imm8 @AL,AH A,ear A,eam Ri,ear Ri,eam
2 3 1 2 2+ 2 2 2 3 1 2 3+ 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+
3 4 2 2 3+(a) 3 2 3 10 1 3 4 2 2 3+(a) 3 2 3 5 10 3 4 2 2 3+(a) 3 10 3 4+(a) 4 5+(a) 2 5 5 2 4+(a) 3 4 5+(a) 7 9+(a)
0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2
(b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2x(b) 0 2x(b)
byte (A) <-- (dir) byte (A) <-- (addr16) byte (A) <-- (Ri) byte (A) <-- (ear) byte (A) <-- (eam) byte (A) <-- (io) byte (A) <-- imm8 byte (A) <-- ((A)) byte (A) <-- ((RLi)+disp8) byte (A) <-- imm4 byte (A) <-- (dir) byte (A) <-- (addr16) byte (A) <-- (Ri) byte (A) <-- (ear) byte (A) <-- (eam) byte (A) <-- (io) byte (A) <-- imm8 byte (A) <-- ((A)) byte (A) <-- ((RWi)+disp8) byte (A) <-- ((RLi)+disp8 byte (dir) <-- (A) byte (addr16) <-- (A) byte (Ri) <-- (A) byte (ear) <-- (A) byte (eam) <-- (A) byte (io) <-- (A) byte ((RLi)+disp8) <-- (A) byte (Ri) <-- (ear) byte (Ri) <-- (eam) byte (ear) <-- (Ri) byte (eam) <-- (Ri) byte (Ri) <-- imm8 byte (io) <-- imm8 byte (dir) <-- imm8 byte (ear) <-- imm8 byte (eam) <-- imm8 byte ((A)) <-- (AH) byte (A) <--> (ear) byte (A) <--> (eam) byte (Ri) <--> (ear) byte (Ri) <--> (eam)
Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X Z Z -
* * * * * * * * * * * * * * * * * * -
-
-
* * * * * * * * * R -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * -
* * * * * * * * * * * * * * * * * * * * * * * * -
-
-
-
See Tables B.5-1 and B.5 -2 for information on (a) to (d) in the table.
427
APPENDIX B INSTRUCTIONS
Table B.8-2 38 Transfer Instructions (byte)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW XCHW XCHW XCHW XCHW MOVL MOVL MOVL MOVL MOVL
A,dir A,addr16 A,SP A,RWi A,ear A,eam A,io A,@A A,#imm16 A,@RWi+disp8 A,@RLi+disp8 dir,A addr16,A SP,A RWi,A ear,A eam,A io,A @RWi+disp8,A @RLi+disp8,A RWi,ear RWi,eam ear,Rwi eam,Rwi RWi,#imm16 io,#imm16 ear,#imm16 eam,#imm16 @AL,AH/MOVW @A,T A,ear A,eam RWi, ear RWi, eam A,ear A,eam A,#imm32 ear,A eam,A
2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2+ 5 2 2+
3 4 1 2 2 3+(a) 3 3 2 5 10 3 4 1 2 2 3+(a) 3 5 10 3 4+(a) 4 5+(a) 2 5 2 4+(a) 3 4 5+(a) 7 9+(a) 4 5+(a) 3 4 5+(a)
0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 2 0 0 2 0
(c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 x (c) 0 2 x (c) 0 (d) 0
word (A) <-- (dir) word (A) <-- (addr16) word (A) <-- (SP) word (A) <-- (RWi) word (A) <-- (ear) word (A) <-- (eam) word (A) <-- (io) word (A) <-- ((A)) word (A) <-- imm16 word (A) <-- ((RWi)+disp8) word (A) <-- ((RLi)+disp8) word (dir) <-- (A) word (addr16) <-- (A) word (SP) <-- (A) word (RWi) <-- (A) word (ear) <-- (A) word (eam) <-- (A) word (io) <-- (A) word ((RWi)+disp8) <-- (A) word ((RLi)+disp8) <-- (A) word (RWi) <-- (ear) word (RWi) <-- (eam) word (ear) <-- (RWi) word (eam) <-- (RWi) word (RWi) <-- imm16 word (io) <-- imm16 word (ear) <-- imm16 word (eam) <-- imm16 word ((A)) <-- (AH) word (A) <--> (ear) word (A) <-- >(eam) word (RWi) <--> (ear) word (RWi) <--> (eam) long (A) <-- (ear) long (A) <-- (eam) long (A) <-- imm32 long (ear1) <-- (A) long
-
* * * * * * * * * * -
-
-
-
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
-
-
-
(d)
(eam1) <-- (A)
See Tables B.5-1 and B.5 -2 for information on (a) to (d) in the table.
428
APPENDIX B INSTRUCTIONS
Table B.8-3 42 Addition/subtraction Instructions (byte, word, long word)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC
A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A
2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1
2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3 2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3
0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0
0 (b) 0 (b) 0 2x(b) 0 0 (b) 0 0 (b) 0 (b) 0 2x(b) 0 0 (b) 0
byte (A) <-- (A) + imm8 byte (A) <-- (A) + (dir) byte (A) <-- (A) + (ear) byte (A) <-- (A) + (eam) byte (ear) <-- (ear) + (A) byte (eam) <-- (eam) + (A) byte (A) <-- (AH) + (AL) + (C) byte (A) <-- (A) + (ear)+ (C) byte (A) <-- (A) + (eam)+ (C) byte (A) <-- (AH) + (AL) + (C) (decimal) byte (A) <-- (A) - imm8 byte (A) <-- (A) - (dir) byte (A) <-- (A) - (ear) byte (A) <-- (A) - (eam) byte (ear) <-- (ear) - (A) byte (eam) <-- (eam) - (A) byte (A) <-- (AH) - (AL) - (C) byte (A) <-- (A) - (ear) - (C) byte (A) <-- (A) - (eam) - (C) byte (A) <-- (AH) - (AL) - (C) (decimal) word (A) <-- (AH) + (AL) word (A) <-- (A) + (ear) word (A) <-- (A) + (eam) word (A) <-- (A) + imm16 word (ear) <-- (ear) + (A) word (eam) <-- (eam) + (A) word (A) <-- (A) + (ear) + (C) word (A) <-- (A) + (eam) + (C) word (A) <-- (AH) - (AL) word (A) <-- (A) - (ear) word (A) <-- (A) - (eam) word (A) <-- (A) - imm16 word (ear) <-- (ear) - (A) word (eam) <-- (eam) - (A) word (A) <-- (A) - (ear) - (C) word (A) <-- (A) - (eam) - (C) long (A) <-- (A) + (ear) long (A) <-- (A) + (eam) long (A) <-- (A) + imm32 long (A) <-- (A) - (ear) long (A) <-- (A) - (eam) long (A) <-- (A) - imm32
Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
-
-
-
-
* * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * *
* * -
ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW ADDL ADDL ADDL SUBL SUBL SUBL
A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A,ear A,eam A,#imm32 A,ear A,eam A,#imm32
1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 2+ 5 2 2+ 5
2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 6 7+(a) 4 6 7+(a) 4
0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0
0 0 (c) 0 0 2x(c) 0 (c) 0 0 (c) 0 0 2x(c) 0 (c) 0 (d) 0 0 (d) 0
-
-
-
-
-
* * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * *
* * -
See Tables B.5-1 and for information on (a) to (d) in the table. Table B.8-4 12 Increment/decrement Instructions (byte, word, long word)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
INC INC DEC DEC INCW INCW DECW DECW
ear eam ear eam ear eam ear eam
2 2+ 2 2+ 2 2+ 2 2+
3 5+(a) 3 5+(a) 3 5+(a) 3 5+(a)
2 0 2 0 2 0 2 0
0 2x(b) 0 2x(b) 0 2x(c) 0 2x(c)
byte (ear) <-- (ear) + 1 byte (eam) <-- (eam) + 1 byte (ear) <-- (ear) - 1 byte (eam) <-- (eam) - 1 word (ear) <-- (ear) + 1 word (eam) <-- (eam) + 1 word (ear) <-- (ear) - 1 word (eam) <-- (eam) - 1
-
-
-
-
-
* * * * * * * *
* * * * * * * *
* * * * * * * *
-
* * * *
429
APPENDIX B INSTRUCTIONS Table B.8-4 12 Increment/decrement Instructions (byte, word, long word) (Continued)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
INCL INCL DECL DECL
ear eam ear eam
2 2+ 2 2+
7 9+(a) 7 9+(a)
4 0 4 0
0 2x(d) 0 2x(d)
long (ear) <-- (ear) + 1 long (eam) <-- (eam) + 1 long (ear) <-- (ear) - 1 long (eam) <-- (eam) - 1
-
-
-
-
-
* * * *
* * * *
* * * *
-
* *
See Tables B.5-1 and B.5 -2for information on (a) to (d) in the table. Table B.8-5 11 Compare Instructions (byte, word, long word)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL
A A,ear A,eam A,#imm8 A A,ear A,eam A,#imm16 A,ear A,eam A,#imm32
1 2 2+ 2 1 2 2+ 3 2 2+ 5
12 3+(a) 2
0 1 0 0 0 1 0 0 2 0 0
0 0 (b) 0 0 0 (c) 0 0 (d) 0
byte (AH) - (AL) byte (A) - (ear) byte (A) - (eam) byte (A) - imm8 word (AH) - (AL) word (A) - (ear) word (A) - (eam) word (A) - imm16 long (A) - (ear) long (A) - (eam) long (A) - imm32
-
-
-
-
-
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
-
12 3+(a) 2
6 7+(a) 3
See Tables B.5-1and B.5 -2for information on (a) to (d) in the table. Table B.8-6 11 unsigned multiplication/division instructions (word, long word)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
DIVU DIVU DIVU DIVUW DIVUW
A A,ear A,eam A,ear A,eam
1 2 2+ 2 2+
*1 *2 *3 *4 *5
0 1 0 1 0
0 0 *6 0 *7
word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) word (A) / byte (eam) quotient --> byte (A) remainder --> byte (eam) long (A) / word (ear) quotient --> word(A) remainder --> word(ear) long (A) / word (eam) quotient --> word(A) remainder --> word(eam) byte (AH) * byte (AL) --> word (A) byte (A) * byte (ear) --> word (A) byte (A) * byte (eam) --> word (A) word (AH) * word (AL) --> Long (A) word (A) * word (ear) --> Long (A) word (A) * word (eam) --> Long (A)
-
-
-
-
-
-
-
* * * * *
* * * * *
-
MULU MULU MULU MULUW MULUW MULUW
A A,ear A,eam A A,ear A,eam
1 2 2+ 1 2 2+
*8 *9 *10 *11 *12 *13
0 1 0 0 1 0
0 0 (b) 0 0 (c)
-
-
-
-
-
-
-
-
-
-
*1 3: Division by 0 7: Overflow 15: Normal *2 4: Division by 0 8: Overflow 16: Normal *3 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal *4 4: Division by 0 7: Overflow 22: Normal *5 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal *6 (b): Division by 0 or overflow 2x(b): Normal *7 (c): Division by 0 or overflow 2x(c): Normal 430
APPENDIX B INSTRUCTIONS *8 3: Byte (AH) is 0. 7: Byte (AH) is not 0. *9 4: Byte (ear) is 0. 8: Byte (ear) is not 0. *10 5+(a): Byte (eam) is 0. 9+(a): Byte (eam) is not 0. *11 3: Word (AH) is 0. 11: Word (AH) is not 0 *12 4: Word (ear) is 0. 12: Word (ear) is not 0. *13 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0. Note: See Tables B.5-1 and B.5-2 for information on (a) to (d) in the table.
Table B.8-7 39 Logic 1 Instructions (byte, word)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW
A,#imm8 A,ear A,eam ear,A eam,A A,#imm8 A,ear A,eam ear,A eam,A A,#imm8 A,ear A,eam ear,A eam,A A ear eam A A,#imm16 A,ear A,eam ear,A eam,A A A,#imm16 A,ear A,eam ear,A eam,A A A,#imm16 A,ear A,eam ear,A eam,A A ear eam
2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+
2 3 4+(a) 3 5+(a) 2 3 4+(a) 3 5+(a) 2 3 4+(a) 3 5+(a) 2 3 5+(a) 2 2 3 4+(a) 3 5+(a) 2 2 3 4+(a) 3 5+(a) 2 2 3 4+(a) 3 5+(a) 2 3 5+(a)
0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0
0 0 (b) 0 2x(b) 0 0 (b) 0 2x(b) 0 0 (b) 0 2x(b) 0 0 2x(b) 0 0 0 (c) 0 2x(c) 0 0 0 (c) 0 2x(c) 0 0 0 (c) 0 2x(c) 0 0 2x(c)
byte (A) <-- (A) and imm8 byte (A) <-- (A) and (ear) byte (A) <-- (A) and (eam) byte (ear) <-- (ear)and (A) byte (eam) <-- (eam)and (A) byte (A) <-- (A) or imm8 byte (A) <-- (A) or (ear) byte (A) <-- (A) or (eam) byte (ear) <-- (ear)or (A) byte (eam) <-- (eam)or (A) byte (A) <-- (A) xor imm8 byte (A) <-- (A) xor (ear) byte (A) <-- (A) xor (eam) byte (ear) <-- (ear)xor (A) byte (eam) <-- (eam)xor (A) byte (A) <-- not (A) byte (ear) <-- not (ear) byte (eam) <-- not (eam) word (A) <-- (AH) and (A) word (A) <-- (A) and imm16 word (A) <-- (A) and (ear) word (A) <-- (A) and (eam) word (ear) <-- (ear)and (A) word (eam) <-- (eam)and (A) word (A) <-- (AH) or (A) word (A) <-- (A) or imm16 word (A) <-- (A) or (ear) word (A) <-- (A) or (eam) word (ear) <-- (ear)or (A) word (eam) <-- (eam)or (A) word (A) <-- (AH) xor (A) word (A) <-- (A) xor imm16 word (A) <-- (A) xor (ear) word (A) <-- (A) xor (eam) word (ear) <-- (ear)xor (A) word (eam) <-- (eam)xor (A) word (A) <-- not (A) word (ear) <-- not (ear) word (eam) <-- not (eam)
-
-
-
-
-
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
-
* * * * * * * *
431
APPENDIX B INSTRUCTIONS See Tables B.5-1 and B.5-2 for information on (a) to (d) in the table. Table B.8-8 Six Logic 2 Instructions (long word)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
ANDL ANDL ORL ORL XORL XORL
A,ear A,eam A,ear A,eam A,ear A,eam
2 2+ 2 2+ 2 2+
6 7+(a) 6 7+(a) 6 7+(a)
2 0 2 0 2 0
0 (d) 0 (d) 0 (d)
long (A) <-- (A) and (ear) long (A) <-- (A) and (eam) long (A) <-- (A) or (ear) long (A) <-- (A) or (eam) long (A) <-- (A) xor (ear) long (A) <-- (A) xor (eam)
-
-
-
-
-
* * * * * *
* * * * * *
R R R R R R
-
-
See Tables B.5-1 and B.5-2 for information on (a) to (d) in the table. Table B.8-9 Six Sign Inversion Instructions (byte, word)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
NEG NEG NEG NEGW NEGW NEGW
A ear eam A ear eam
1 2 2+ 1 2 2+
2 3 5+(a) 2 3 5+(a)
0 2 0 0 2 0
0 0 0x(b) 0 0 2x(c)
byte (A) <-- 0 - (A) byte (ear) <-- 0 - (ear) byte (eam) <-- 0 - (eam) word (A) <-- 0 - (A) word (ear) <-- 0 - (ear) word (eam) <-- 0 - (eam)
X -
-
-
-
-
* * * * * *
* * * * * *
* * * * * *
* * * * * *
* *
See Tables B.5-1 and B.5-2 for information on (a) to (d) in the table. Table B.8-10 One Normalization Instruction (long word)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
NRML
A,R0
2
*1
1
0
long (A) <-- Shifts to the position where '1' is set for the first time. byte (RD) <-- Shift count at that time
-
-
-
-
-
-
*
-
-
-
See Tables B.5-1 and B.5-2 for information on (a) to (d) in the table. Table B.8-11 18 Shift Instructions (byte, word, long word)
Mnemonic # ~ R G B Operation L H A H I S T N Z V C R M W
RORC ROLC RORC RORC ROLC ROLC ASR LSR LSL
A A ear eam ear eam A,R0 A,R0 A,R0
2 2 2 2+ 2 2+ 2 2 2
2 2 3 5+(a) 3 5+(a) *1 *1 *1
0 0 2 0 2 0 1 1 1
0 0 0 2x(b) 0 2x(b) 0 0 0
byte (A) <-- With right rotation carry byte (A) <-- With left rotation carry byte (ear) <-- With right rotation carry byte (eam) <-- With right rotation carry byte (ear) <-- With left rotation carry byte (eam) <-- With left rotation carry byte (A) <-- Arithmetic right shift (A, 1 bit) byte (A) <-- Logical right barrel shift (A, R0) byte (A) <-- Logical left barrel shift (A, R0)
-
-
-
-
-
* * * * * * * * *
* * * * * * * * *
-
* * * * * * * * *
* * -
432
APPENDIX B INSTRUCTIONS Table B.8-11 18 Shift Instructions (byte, word, long word) (Continued)
Mnemonic # ~ R G B Operation L H A H I S T N Z V C R M W
ASRW LSRW LSLW ASRW LSRW LSLW ASRL LSRL LSLL
A A/SHRW A A/SHLW A A,R0 A,R0 A,R0 A,R0 A,R0 A,R0
1 1 1 2 2 2 2 2 2
2 2 2 *1 *1 *1 *2 *2 *2
0 0 0 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0
word (A) <-- Arithmetic right shift (A, 1 bit) word (A) <-- Logical right shift (A, 1 bit) word (A) <-- Logical left shift (A, 1 bit) word (A) <-- Arithmetic right barrel shift (A, R0) word (A) <-- Logical right barrel shift (A, R0) word (A) <-- Logical left barrel shift (A, R0) long (A) <-- Arithmetic right barrel shift (A, R0) long (A) <-- Logical right barrel shift (A, R0) long (A) <-- Logical left barrel shift (A, R0)
-
-
-
-
* * * * * * -
* R * * * * * * *
* * * * * * * * *
-
* * * * * * * * *
-
*1 6 when R0 is 0; otherwise, 5 + (R0) *2 6 when R0 is 0; otherwise, 5 + (R0) See Tables B.5-1 and B.5-2 for information on (a) to (d) in the table. Table B.8-12 31 Branch 1 Instructions
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
BZ/BEQ BNZ/BNE BC/BLOB NC/BHS BN BP BV BNV BT BNT BLT BGE BLE BGT BLS BHI BRA JMP JMP JMP JMP JMPP JMPP JMPP
rel rel rel rel rel rel rel rel rel rel rel rel rel rel rel rel rel @A addr16 @ear @eam @ear *3 @eam *3 addr24
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4
*1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+(a) 5 6+(a) 4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0
Branch on (Z) = 1 Branch on (Z) = 0 Branch on (C) = 1 Branch on (C) = 0 Branch on (N) = 1 Branch on (N) = 0 Branch on (V) = 1 Branch on (V) = 0 Branch on (T) = 1 Branch on (T) = 0 Branch on (V) xor (N) = 1 Branch on (V) xor (N) = 0 ((V) xor (N)) or (Z) = 1 ((V) xor (N)) or (Z) = 0 Branch on (C) or (Z) = 1 Branch on (C) or (Z) = 0 Unconditional branch word (PC) <-- (A) word (PC) <-- addr16 word (PC) <-- (ear) word (PC) <-- (eam) word (PC) <-- (ear), (PCB) <-- (ear+2) word (PC) <-- (eam), (PCB) <-- (eam+2) word(PC) <-- ad24 0-15,(PCB) <-- ad24 16-23 word (PC) <-- (ear) word (PC) <-- (eam) word (PC) <-- addr16 Vector call instruction word(PC) <-- (ear)0-15,(PCB) <-(ear)16-23 word(PC) <-- (eam)0-15,(PCB) <-(eam)16-23 word(PC) <-- addr0-15, (PCB) <-addr16-23
-
-
-
-
-
-
-
-
-
-
CALL CALL CALL CALLV CALLP CALLP
@ear *4 @eam *4 addr16 *5 #vct4 *5 @ear *6 @eam *6
2 2+ 3 1 2 2+
6 7+(a) 6 7 10 11+(a)
1 0 0 0 2 0
(c) 2x(c) (c) 2x(c) 2x(c) *2
-
-
-
-
-
-
-
-
-
-
CALLP
addr24 *7
4
10
0
2x(c)
-
-
-
-
-
-
-
-
-
-
*1 4 when a branch is made; otherwise, 3 *2 3 x (c) + (b) *3 Read (word) of branch destination address *4 W: Save to stack (word) R: Read (word) of branch destination address
433
APPENDIX B INSTRUCTIONS *5 Save to stack (word) *6 W: Save to stack (long word) R: Read ( long word) of branch destination address *7 Save to stack (long word) Note: See Tables B.5-1and B.5-2 for information on (a) to (d) in the table. Table B.8-13 19 Branch 2 Instructions
Mnemonic # ~ R G B Operation L H A H I S T N Z V C R M W
CBNE CWBNE CBNE CBNE CWBNE CWBNE
A,#imm8,rel A,#imm16,rel ear,#imm8,rel eam,#imm8,rel *9 ear,#imm16,rel eam,#imm16,rel*9
3 4 4 4+ 5 5+
*1 *1 *2 *3 *4 *3
0 0 1 0 1 0
0 0 0 (b) 0 (c)
Branch on byte (A) not equal to imm8 Branch on word (A) not equal to imm16 Branch on byte (ear) not equal to imm8 Branch on byte (eam) not equal to imm8 Branch on word (ear) not equal to imm16 Branch on word (eam) not equal to imm16 Branch on byte (ear) = (ear) - 1, (ear)not equal to 0 Branch on byte (eam) = (eam) - 1, (eam) not equal to 0 Branch on word (ear) = (ear) - 1, (ear) not equal to 0 Branch on word (eam) = (eam) - 1, (eam) not equal to 0 Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt Saves the old frame pointer in the stack upon entering the function, then sets the new frame pointer and reserves the local pointer area. Recovers the old frame pointer from the stack upon exiting the function. Return from subroutine Return from subroutine
-
-
-
-
-
* * * * * *
* * * * * *
* * * * * *
* * * * * *
-
DBNZ DBNZ
ear,rel eam,rel
3 3+
*5 *6
2 2
0 2x(b)
-
-
-
-
-
* *
* * * *
-
*
DWBNZ DWBNZ
ear,rel eam,rel
3 3+
*5 *6
2 2
0 2x(c)
-
-
-
-
-
* *
* *
* *
-
*
INT INT INTP INT9 RETI ILINK
#vct8 addr16 addr24
2 3 4 1 1 2
20 16 17 20 15 6
0 0 0 0 0 0
8x(c) 6x(c) 6x(c) 8x(c) 6x(c) (c)
-
-
R R R R * -
S S S S * -
* -
* -
* -
* -
* -
-
IUNLINK
1
5
0
(c)
-
-
-
-
-
-
-
-
-
-
RET RETP
*7 *8
1 1
4 6
0 0
(c) (d)
-
-
-
-
-
-
-
-
-
-
*1 5 when a branch is made; otherwise, 4 *2 13 when a branch is made; otherwise, 12 *3 7+(a) when a branch is made; otherwise, 6+(a) *4 8 when a branch is made; otherwise, 7 *5 7 when a branch is made; otherwise, 6 *6 8+(a) when a branch is made; otherwise, 7+(a) *7 Return from stack (word) *8 Return from stack (long word) *9 Do not use RWj+ addressing mode with the CBNE or CWBNE instruction. Note: See Tables B.4 and B.5 for information on (a) to (d) in the table.
434
APPENDIX B INSTRUCTIONS See Tables B.5-1and B.5-2 for information on (a) to (d) in the table. Table B.8-14 31 28 Other Control Instructions (byte, word, long word)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
PUSHW PUSHW PUSHW PUSHW POPW POPW POPW POPW JCTX AND OR MOV MOV MOVEA MOVEA MOVEA MOVEA ADDSP ADDSP MOV MOV NOP ADB DTB PCB SPB NCC CMR
A AH PS rlst A AH PS rlst @A CCR,#imm8 CCR,#imm8 RP,#imm8 ILM,#imm8 RWi,ear RWi,eam A,ear A,eam #imm8 #imm16 A,brg1 brg2,A
1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1
4 4 4 *3 3 3 4 *2 14 3 3 2 2 3 2+(a) 1 1+(a) 3 3 *1 1 1 1 1 1 1 1 1
0 0 0
(c) (c) (c) *4 (c) (c) (c) *4 6x(c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
word (SP) <-- (SP) - 2 , ((SP)) <-- (A) word (SP) <-- (SP) - 2 , ((SP)) <-- (AH) word (SP) <-- (SP) - 2 , ((SP)) <-- (PS) (SP) <-- (SP) - 2n , ((SP)) <-- (rlst) word (A) <-- ((SP)) , (SP) <-- (SP) + 2 word (AH) <-- ((SP)) , (SP) <-- (SP) + 2 word (PS) <-- ((SP)) , (SP) <-- (SP) + 2 (rlst) <-- ((SP)) , (SP) <-- (SP) Context switch instruction byte (CCR) <-- (CCR) and imm8 byte(CCR) <-- (CCR) or imm8 byte (RP) <-- imm8 byte (ILM)A(c) imm8 word (RWi) <-- ear word (RWi) <-- eam word (A) <-- ear word (A) <-- eam word (SP) <-- ext(imm8) word (SP) <-- imm16 byte (A) <-- (brg1) byte (brg2) <-- (A) No operation Prefix code for AD space access Prefix code for DT space access Prefix code for PC space access Prefix code for SP space access Prefix code for flag no-change Prefix code for common register bank
Z -
* * * * -
* * * * -
* * * * -
* * * * -
* * * * * * -
* * * * * * -
* * * * -
* * * * -
-
0 0 0
0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
*1 PCB, ADB, SSB, USB: 1, DTB, DPR: 2 *2 7 + 3x(POP count) + 2x(POP last register number), 7 when RLST = 0 (no transfer register) *3 29 + 3x(PUSH count) - 3x(PUSH last register number), 8 when RLST = 0 (no transfer register) *4 (POP count)x(c) or (PUSH count)x(c) *5 (POP count) or (PUSH count) Note: See Tables B.5-1 and B.5-2 for information on (a) to (d) in the table. Table B.8-15 21 Bit Operand Instructions
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
MOVB MOVB MOVB MOVB MOVB MOVB
A,dir:bp A,addr16:bp A,io:bp dir:bp,A addr16:bp,A io:bp,A
3 4 3 3 4 3
5 5 4 7 7 6
0 0 0 0 0 0
(b) (b) (b) 2x(b) 2x(b) 2x(b)
byte (A) <-- ( dir:bp )b byte (A) <-- ( addr16:bp )b byte (A) <-- ( io:bp )b bit ( dir:bp )b <-- (A) bit ( addr16:bp )b <-- (A) bit ( io:bp )b <-- (A)
Z Z Z -
* * * -
-
-
-
* * * * * *
* * * * * *
-
-
* * *
435
APPENDIX B INSTRUCTIONS Table B.8-15 21 Bit Operand Instructions (Continued)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
SETB SETB SETB CLRB CLRB CLRB BBC BBC BBC BBS BBS BBS SBBS WBTS WBTC
dir:bp addr16:bp io:bp dir:bp addr16:bp io:bp dir:bp,rel addr16:bp,rel io:bp,rel dir:bp,rel addr16:bp,rel io:bp,rel addr16:bp,rel io:bp io:bp
3 4 3 3 4 3 4 5 4 4 5 4 5 3 3
7 7 7 7 7 7 *1 *1 *2 *1 *1 *1 *3 *4 *4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2x(b) 2x(b) 2x(b) 2x(b) 2x(b) 2x(b) (b) (b) (b) (b) (b) (b) 2x(b) *5 *5
bit ( dir:bp )b <-- 1 bit ( addr16:bp )b <-- 1 bit ( io:bp )b <-- 1 bit ( dir:bp )b <-- 0 bit ( addr16:bp )b <-- 0 bit ( io:bp )b <-- 0 Branch on (dir:bp) b = 0 Branch on (addr16:bp) b = 0 Branch on (io:bp) b = 0 Branch on (dir:bp) b = 1 Branch on (addr16:bp) b = 1 Branch on (io:bp) b = 1 Branch on (addr16:bp) b = 1, bit = 1 Waits until (io:bp) b = 1 Waits until (io:bp) b = 0
-
-
-
-
-
-
* * * * * * * -
-
-
* * * * * * * -
*1 8 when a branch is made; otherwise, 7 *2 7 when a branch is made; otherwise, 6 *3 10 when the condition is met; otherwise 9 *4 Undefined count *5 Until the condition is met( dir:bp )b Table B.8-16 Six Accumulator Operation Instructions (byte, word)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
SWAP SWAPW/XCHW A,T EXT EXTW ZEXT ZEXTW
1 1 1 1 1 1
3 2 1 2 1 1
0 0 0 0 0 0
0 0 0 0 0 0
byte (A)0-7 <--> (A)8-15 word (AH) <--> (AL) Byte sign extension Word sign extension Byte zero extension Word zero extensionbyte
X Z -
* X -
Z
-
-
* * R R
* * * *
-
-
-
See Tables B.5-1and B.5-2 for information on (a) to (d) in the table. Table B.8-17 Ten String Instructions
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
MOVS / MOVSI MOVSD SCEQ / SCEQI SCEQD FILS / FILSI
2 2 2 2 2
*2 *2 *1 *1 6m+6
*3 *3 *4 *4 *3
byte transfer @AH+ <-- @AL+, counter = RW0 byte transfer @AH- <-- @AL-, counter = RW0 byte search @AH+ <-- AL, counter RW0 byte search @AH- <-- AL, counter RW0 byte fill @AH+ <-- AL, counter RW0
-
-
-
-
-
* * *
* * *
* * -
* * -
-
436
APPENDIX B INSTRUCTIONS Table B.8-17 Ten String Instructions (Continued)
Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W
MOVSW / MOVSW MOVSWD
2 2
*2 *2
*6 *6
word transfer @AH+ <-- @AL+, counter = RW0 word transfer @AH- <-- @AL-, counter = RW0 word search @AH+ A| AL, counter = RW0 word search @AH- A| AL, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI SCWEQD
2 2
*1 *1
*7 word fill @AH+ <-- AL, counter = RW0 *7
-
-
-
-
-
* *
* *
* *
* *
-
FILSW / FILSWI
2
6m+6
*6
-
-
-
-
-
*
*
-
-
-
*1 5 when RW0 is 0, 4 + 7 x (RW0) when the counter expires, or 7n + 5 when a match occurs *2 5 when RW0 is 0; otherwise, 4 + 8 x (RW0) *3 (b) x (RW0) + (b) x (RW0) calculate the (b) item individually. *4 (b) x n *5 2 x (R x W0) *6 (c) x (RW0) + (c) x (RW0) calculate the (c) item individually. *7 (c) x n *8 2 x 0(RW0) m: RW0 value (counter value), n: Loop count Note: See Tables B.5-1and B.5-2 for information on (a) to (d) in the table. When the source and destination access different areas, When the source and destination access different areas,
437
APPENDIX B INSTRUCTIONS
B.9
Instruction Map
Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Tables B.9-2 to B.9-21 summarize the F2MC-16LX instruction map.
s Structure of Instruction Map
Figure B.9-1 Structure of Instruction Map
Basic page map : Byte 1
Bit operation instructions
Character string operation instructions
2-byte instructions
ea instructions x 9
: Byte 2
An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2 shows the correspondence between an actual
438
APPENDIX B INSTRUCTIONS instruction code and instruction map. Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map
Some instructions do not contain byte 2. Length varies depending on the instruction. Instruction code Byte 1 Byte 2 Operand Operand ...
[Basic page map]
XY
+Z
[Extended page map] (*1)
UV
+W
*1 The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions. Actually, there are multiple extended page maps for each type of instructions.
An example of an instruction code is shown in Table B.9-1. Table B.9-1 Example of an Instruction Code Instruction Byte 1 (from basic page map) 00 +0=00 30 +4=34 60 +F=6F 70 +0=70 Byte 2 (from extended page map) 00 +0=00 F0 +2=F2
NOP AND A, #8 MOV A, ADB @RW2+d8, rel
439
440
ea instruction 1 ea instruction 2 ea instruction 3 ea instruction 4 ea instruction 5 ea instruction 6 ea instruction 7 ea instruction 8 ea instruction 9
APPENDIX B INSTRUCTIONS Table B.9-2 Basic Page Map
Bit operation instruction
Character string operation instruction
2-byte instruction
APPENDIX B INSTRUCTIONS
Table B.9-3 Bit Operation Instruction Map (first byte = 6CH)
441
APPENDIX B INSTRUCTIONS Table B.9-4 Character String Operation Instruction Map (first byte = 6EH)
442
APPENDIX B INSTRUCTIONS Table B.9-5 2-byte Instruction Map (first byte = 6FH)
443
444
Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited
APPENDIX B INSTRUCTIONS
Table B.9-6 ea Instruction 1 (first byte = 70H)
APPENDIX B INSTRUCTIONS Table B.9-7 ea Instruction 2 (first byte = 71H)
445
APPENDIX B INSTRUCTIONS Table B.9-8 ea Instruction 3 (first byte = 72H)
446
APPENDIX B INSTRUCTIONS Table B.9-9 ea Instruction 4 (first byte = 73H)
447
APPENDIX B INSTRUCTIONS Table B.9-10 ea Instruction 5 (first byte = 74H)
448
APPENDIX B INSTRUCTIONS Table B.9-11 ea Instruction 6 (first byte = 75H)
449
APPENDIX B INSTRUCTIONS Table B.9-12 ea Instruction 7 (first byte = 76H)
450
APPENDIX B INSTRUCTIONS Table B.9-13 ea Instruction 8 (first byte = 77H)
451
APPENDIX B INSTRUCTIONS Table B.9-14 ea Instruction 9 (first byte = 78H)
452
APPENDIX B INSTRUCTIONS Table B.9-15 MOVEA RWi, ea Instruction (first byte = 79H)
453
APPENDIX B INSTRUCTIONS Table B.9-16 MOV Ri, ea Instruction (first byte = 7AH)
454
APPENDIX B INSTRUCTIONS Table B.9-17 MOVW RWi, ea Instruction (first byte = 7BH)
455
APPENDIX B INSTRUCTIONS Table B.9-18 MOV ea, Ri Instruction (first byte = 7CH)
456
APPENDIX B INSTRUCTIONS Table B.9-19 MOVW ea, Rwi Instruction (first byte = 7DH)
457
APPENDIX B INSTRUCTIONS Table B.9-20 XCH Ri, ea Instruction (first byte = 7EH)
458
APPENDIX B INSTRUCTIONS Table B.9-21 XCHW RWi, ea Instruction (first byte = 7FH)
459
APPENDIX C Timing Diagrams in Flash Memory Mode
APPENDIX C Timing Diagrams in Flash Memory Mode
Each timing diagram for the external pins of the MB90F594 in the Flash Memory mode is shown below.
s Data read by Read Access
Figure C-1 Timing Diagram for Read Access
tRC AQ16 to AQ0 tACC CE tOE OE tOEH WE tCE tOH High impedance DQ7 to DQ0 High impedance Output defined tDF Address stable
s Write, Data polling, Read (WE control)
Figure C-2 Write Data polling Read (WE control)
Third bus cycle AQ18 to AQ0 Data polling 7AAAAH tWC CE tGHWL OE tWP tWHWH1 WE tCS tWPH tDH A0H tDS tOH 5.0 V tCE PD DQ7 DOU
T
PA tAS tAH
PA tRC
tOE tDF
DQ7 to DQ0
PA: Write address PD: Write data DQ7: Reverse output of write data DOUT: Output of write data
Note: The last two bus cycle sequences out of the four are described. 460
APPENDIX C Timing Diagrams in Flash Memory Mode s Write Data Polling Read (CE control)
Figure C-3 Timing Diagram for Write Access (CE Control)
Third bus cycle Data polling AQ18 to AQ0 7AAAAH tWC tWH WE tGHWL OE tCP tWHWH1 CE tWS A0H DQ7 to DQ0 tDS 5.0 V tCPH tDH PD DQ7 DOU
T
PA tAS tAH
PA
PA: Write address PD: Write data DQ7: Reverse output of write data DOUT: Output of write data
Note: The last two bus cycle sequences out of the four are described. s Chip Erase/sector Erase Command Sequence
Figure C-4 Timing Diagram for Write Access (Chip Erasing/Sector Erasing)
tAS AQ18 to AQ0 7AAAAH tAH 75555H 7AAAAH 7AAAAH 75555H SA*
CE tGHWL OE tWP WE tWPH tCS tDH AAH tDS 55H 80H AAH 55H 10H/30H
DQ7 to DQ0
VCC tVCS
Note*: SA is the sector address at sector erasing. 7AAAAH (or 6AAAAH) is the address at chip erasing.
461
APPENDIX C Timing Diagrams in Flash Memory Mode s Data Polling Figure C-5 Timing Diagram for Data Polling
tCH CE tOE OE tOEH WE tDF
tCE * DQ7 tWHWH1 or tWHWH2 DQ6 to DQ0 DQ6 to DQ0 = Invalid tOE DQ7
tOH High impedance DQ7 = Valid data
DQ6 to DQ0 = Valid data
Note*: DQ7 is valid data (The device terminates automatic operation). s Toggle Bit Figure C-6 Timing Diagram for Toggle Bit
CE tOE H WE tOES OE * Data (DQ7 to DQ0) DQ6 = Toggle DQ6 = Toggle
DQ6 = Stop toggling
DQ7 to DQ0 = Valid
tOE
Note*: DQ6 stops toggling (The device terminates automatic operation). s RY/BY Timing During Writing/erasing Figure C-7 Timing Diagram for Output of RY/BY Signal during Writing/Erasing
CE Rising edge of last write pulse WE
Writing or erasing
RY/BY
tBUSY
462
APPENDIX C Timing Diagrams in Flash Memory Mode s RST and RY/BY timing
Figure C-8 Timing Diagram for Output of RY/BY Signal at Hardware Reset
CE
RY/BY tRP RST
tReady
s Enable Sector Protect/verify Sector Protect
Figure C-9 Enable Sector Protect/Verify Sector Protect
AQ18 to AQ9 SAx SAy
AQ8, AQ2, and AQ1
(AQ8, AQ2, AQ1) = (0, 1, 0)
MD0 12 V 5V
MD2 12 V 5V tVLHT OE tVLHT
WE
tWPP
CE tCSP
tOESP
DQ7 to DQ0 01H tOE
SAx: First sector address SAy: Next sector address
463
APPENDIX C Timing Diagrams in Flash Memory Mode s Temporary Sector Protect Cancellation
Figure C-10 Temporary Sector Protect Cancellation
Write/erase command sequence
464
APPENDIX D List of MB90590 Interrupt Vectors
APPENDIX D List of MB90590 Interrupt Vectors
The interrupt vector table to be referenced for interrupt processing is allocated to FFFC00H to FFFFFFH in the memory area and also used for software interrupts.
s List of MB90590 Interrupt Vectors Table D-1 lists the interrupt vectors for the MB90590 series. Table D-1 MB90590 Interrupt Vectors Software interrupt instruction INT 0 . . . INT 7 INT 8 INT 9 INT 10 INT 11 INT 12 INT 13 INT 14 INT 15 INT 16 INT 17 INT 18 INT 19 INT 20 INT 21 INT 22 INT 23 INT 24 INT 25 Vector address L FFFFECH . . . FFFFE0H FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H Vector address M FFFFEDH . . . FFFFE1H FFFFDDH FFFFD9H FFFFD5H FFFFD1H FFFFCDH FFFFC9H FFFFC5H FFFFC1H FFFFBDH FFFFB9H FFFFB5H FFFFB1H FFFFADH FFFFA9H FFFFA5H FFFFA1H FFFF9DH FFFF99H Vector address H FFFFEEH . . . FFFFE2H FFFFDEH FFFFDAH FFFFD6H FFFFD2H FFFFCEH FFFFCAH FFFFC6H FFFFC2H FFFFBEH FFFFBAH FFFFB6H FFFFB2H FFFFAEH FFFFAAH FFFFA6H FFFFA2H FFFF9EH FFFF9AH Mode register Unused . . . Unused FFFFDF Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Interrupt No. #0 . . . #7 #8 #9 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 None (RESET vector) ROM correction Time base timer External interrupt (INT0 to INT7) CAN 0 RX CAN 0 TX/NS CAN 1 RX CAN 1 TX/NS PPG 0/1 PPG 2/3 PPG 4/5 PPG 6/7 PPG 8/9 PPG A/B 16-bit reload timer 0 16-bit reload timer 1 Input capture 0/1 Hardware interrupt
None . . .
465
APPENDIX D List of MB90590 Interrupt Vectors Table D-1 MB90590 Interrupt Vectors (Continued) Software interrupt instruction INT 26 INT 27 INT 28 INT 29 INT 30 INT 31 INT 32 INT 33 INT 34 INT 35 INT 36 INT 37 INT 38 INT 39 INT 40 INT 41 INT 42 INT 43 . . . INT 254 INT 255 Vector address L FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H FFFF50H . . . FFFC04H FFFC00H Vector address M FFFF95H FFFF91H FFFF8DH FFFF89H FFFF85H FFFF81H FFFF7DH FFFF79H FFFF75H FFFF71H FFFF6DH FFFF69H FFFF65H FFFF61H FFFF5DH FFFF59H FFFF55H FFFF51H . . . FFFC05H FFFC01H Vector address H FFFF96H FFFF92H FFFF8EH FFFF8AH FFFF86H FFFF82H FFFF7EH FFFF7AH FFFF76H FFFF72H FFFF6EH FFFF6AH FFFF66H FFFF62H FFFF5EH FFFF5AH FFFF56H FFFF52H . . . FFFC06H FFFC02H Mode register Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused . . . Unused Unused Interrupt No. #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 #43 . . . #254 #255 None None Hardware interrupt
Output compare 0/1 Input capture 2/3 Output compare 2/3 Input capture 4/5 Output compare 4/5 A/D converter I/O timer/watch-dog timer Serial I/O Sound generator UART 0 RX UART 0 TX UART 1 RX UART 1 TX UART 2 RX UART 2 TX Flash Memory Delayed interrupt None . . .
s Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers Table D-2 summarizes the relationships among the interrupt causes, interrupt vectors, and
466
APPENDIX D List of MB90590 Interrupt Vectors interrupt control registers of the MB90595 series. Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers EI2OS clear N N N N Y1 N N N N N N N N N N Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 N Y1 N Y2 Y1 Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 34 35 36 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH ICR12 ICR11 ICR10 ICR09 ICR08 ICR07 ICR06 ICR05 ICR04 ICR03 ICR02 ICR00 0000B0H Interrupt control register Number -- -- -- Address -- -- --
Interrupt cause
Reset INT9 instruction Exception Time base timer External interrupt (INT0 to INT7) CAN 0 RX CAN 0 TX/NS CAN 1 RX CAN 1 TX/NS PPG 0/1 PPG 2/3 PPG 4/5 PPG 6/7 PPG 8/9 PPG A/B 16-bit reload timer 0 16-bit reload timer 1 Input capture 0/1 Output compare 0/1 Input capture 2/3 Output compare 2/3 Input capture 4/5 Output compare 4/5 A/D converter I/O timer/watchdog time Serial I/O Sound generator UART 0 RX UART 0 TX
ICR01
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
467
APPENDIX D List of MB90590 Interrupt Vectors Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers EI2OS clear Y2 Y1 Y2 Y1 N N Interrupt vector Number 37 38 39 40 41 42 Address FFFF68H FFFF64H FFFF60H ICR14 UART 2 TX Flash memory Delayed interrupt FFFF5CH FFFF58H ICR15 FFFF54H 0000BFH 0000BEH Interrupt control register Number ICR13 Address 0000BDH
Interrupt cause
UART 1 RX UART 1 TX UART 2 RX
Y1: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt request flag. Y2: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt request flag. A stop request is issued. N: An EI2OS interrupt clear signal does not clear the interrupt request flag. Notes: For a peripheral module having two interrupt causes for one interrupt number, an EI2OS interrupt clear signal clears both interrupt request flags. When EI2OS ends, an EI2OS clear signal is sent to every interrupt flag assigned to each interrupt number. EI2OS is activated when one of two interrupts assigned to an interrupt control register (ICR) is caused while EI2OS is enabled. This means that an EI2OS descriptor that should essentially be specific to each interrupt cause is shared by two interrupts. Therefore, while one interrupt is enabled, the other interrupt must be disabled.
468
INDEX
INDEX
The index follows on the next page. This is listed in alphabetic order.
469
INDEX
Index
Numerics 16-bit free-running timer ....................................... 118 16-bit free-running timer block diagram................ 121 16-bit free-running timer operation ....................... 125 16-bit free-running timer timing ............................ 126 16-bit I/O timer, block diagram of .........................119 16-bit reload timer (in internal clock mode), input pin function of .................................................. 150 16-bit reload timer (with event count function), outline of .................................................... 142 16-bit reload timer register ................................... 144 16-bit reload timer, block diagram of.................... 143 16-bit reload timer, internal clock operation of ..... 149 16-bit reload timer, output pin function of............. 153 16-bit reload timer, underflow operation of........... 152 16-bit timer register (TMR)/16-bit reload register (TMRLR), register layout of........................ 148 24-bit operand specification ................................... 21 2M-bit flash memory feature................................. 350 8/16-bit PPG hardware, initial value of ................. 180 8/16-bit PPG, function of ......................................164 8/16-bit PPG, selecting count clock for ................ 177 A A/D converter, block diagram of........................... 196 acceptance filter, setting ......................................311 acceptance filtering .............................................. 307 acceptance mask registers 0 and 1 (AMR0 and AMR1)..................................... 297 acceptance mask select register (AMSR) ............295 accumulator (A) ...................................................... 27 activation .............................................................. 115 address generation type......................................... 19 addressing............................................................ 406 amplitude data register......................................... 333 analog input enable register ................................. 195 B bank addressing type ............................................. 22 bank select prefix ................................................... 35 bit timing register (BTR) ....................................... 281 bit timing, setting .................................................. 311 block diagram ..................................................... 5, 77 buffer address pointer (BAP).................................. 59
bus mode setting bit............................................... 96 bus operation stop (HALT = 0), condition for canceling.................................................... 277 bus operation stop (HALT = 1), state during........ 277 bus operation stop (HALT=1), condition for setting ........................................................ 277 C CAN controller, block diagram of ......................... 263 CAN controller, canceling transmission request from............................................... 305 CAN controller, completing transmission of ......... 306 CAN controller, feature of .................................... 262 CAN controller, reception flowchart of ................. 310 CAN controller, starting transmission of............... 305 CAN controller, transmission flowchart of ............ 306 CE control ............................................................ 461 chip erase/sector erase command sequence ...... 461 CLK asynchronous baud rate .............................. 229 CLK synchronous baud rate ................................ 229 clock generator, note on ........................................ 70 clock selection register (CKSCR)........................... 81 clock selection, status transition of ........................ 92 command sequence table.................................... 357 common register bank prefix (CMR) ...................... 36 compare registers 0 and 1 being used, output waveform sample when ............................. 132 compare registers, output waveform sample with two...................................................... 133 condition code register (CCR)................................ 29 continuous mode.................................................. 206 continuous mode, starting EI2OS in..................... 211 control status register........................................... 136 control status register (ADCS0) ........................... 198 control status register (ADCS1) ........................... 201 control status register (CSR)................................ 274 control status register (FMCS), flash memory ..... 355 control status rgister............................................. 123 conversion data protection................................... 215 counter operation state ........................................ 154 CPU memory space, outline of .............................. 19 D data counter (DCT) ................................................ 58
470
INDEX data frame and remote frame, processing for reception of ................................................ 308 data polling........................................................... 462 data polling flag (DQ7) ......................................... 360 data register ......................................................... 122 data register x (x = 0 to 15) (DTRx) ..................... 303 data registers (ADCR1 and ADCR0) ................... 204 decrement grade register..................................... 334 delayed interrupt cause issuance/cancellation register (DIRR)............................................. 67 delayed interrupt occurrence ................................. 68 delayed interrupt, block diagram of........................ 66 direct addressing.................................................. 408 DLC register x (x = 0 to 15) (DLCRx)................... 302 DTP operation...................................................... 189 DTP request, switching between external interrupt and............................................... 190 DTP/external interrupt, note on using .................. 191 E effective address field .................................. 407, 422 EI2OS operation flow ............................................. 61 EI2OS status register (ISCS) ................................. 60 EI2OS, conversion using...................................... 208 enable sector protect/verify sector protect ........... 463 EPROM memory map.......................................... 340 erasing chip.......................................................... 369 erasing flash memory........................................... 350 erasing sector ...................................................... 370 erasing sector in flash memory ............................ 370 execution cycle count........................................... 419 execution cycle count, calculating........................ 419 extended intelligent I/O service (EI2OS) .......... 41, 56 extended intelligent I/O service descriptor (ISD).... 58 extended serial I/O interface, interrupt function of 258 external clock ....................................................... 232 external event counter ......................................... 151 external interrupt operation .................................. 188 external interrupt request ..................................... 190 external shift clock mode ..................................... 253 F flag change disable prefix (NCC) ........................... 36 flash memory control signal ................................. 353 flash memory mode ............................................. 353 flash memory register .......................................... 350 flash memory write/erase, detailed explanation of ............................................ 365 flash memory, block diagram of entire ................. 351 flash memory, writing to........................................367 flash microcomputer programmer (power supplied from writer), example of minimum connection to ..............................................391 flash microcomputer programmer (user power supply used), example of minimum connection to.389 frame format, setting.............................................311 frequency data register.........................................332 G general-purpose register ........................................26 H hardware interrupt ............................................40, 49 hardware interrupt operation ..................................50 hardware interrupt, occurrence and release of.......51 hardware interrupt, structure of ..............................49 hardware sequence flag .......................................358 hardware standby mode, releasing ........................89 hardware standby mode, transition to ....................89 I I/O map.................................................................394 I/O port..................................................................100 I/O port register.....................................................101 I/O register address pointer (IOA) ..........................58 ID register x (x = 0 to 15) (IDRx)...........................300 IDE register (IDER)...............................................284 indirect addressing ...............................................413 initial condition ......................................................340 input capture.........................................................135 input capture (2 channels per one module) ..........118 input capture block diagram .................................135 input capture data register....................................136 input capture fetch timing, sample of....................138 input capture input timing .....................................139 input data register (UIDR) and output data register (UODR) ......................................................225 input impedance ...................................................195 input-output circuit ..................................................12 instruction map, structure of .................................438 instruction presentation item and symbol, description of ..............................................424 INT9 interrupt........................................................343 intelligent I/O service (EI2OS) function and interrupt ......................................................142 intermittent CPU operation .....................................90 internal and external clock....................................232 internal shift clock mode .......................................253
471
INDEX Interrupt cause, interrupt vector, and interrupt control register ........................................... 466 interrupt control register ....................................... 466 interrupt control register (ICR)................................ 44 interrupt disable instruction .................................... 37 interrupt flow........................................................... 47 interrupt level mask register (ILM).......................... 30 interrupt vector ............................................... 43, 466 interrupt, 8/16-bit PPG ......................................... 179 interrupt, intelligent I/O service (EI2OS) function and ............................................... 142 interrupt/DTP enable register ............................... 186 interval interrupt function ......................................109 L last event indicator register (LEIR) ....................... 278 layout of rate and data register (URD) ................. 226 low power mode control register ............................ 78 low power mode control register (LPMCR) ............ 79 lower-power control circuit, outline of ..................... 76 low-power consumption mode, setting ................. 311 low-power mode control register access, note of ... 84 low-power mode operation ..................................... 83 M machine clock, initializing ....................................... 91 main clock and PLL clock, switching between ....... 91 MB90595 interrupt vector, list of .......................... 465 memory access mode ............................................ 94 memory space map................................................ 20 memory space, multi-byte data allocation in .......... 24 message buffer .................................................... 299 message buffer (data register), list of...................271 message buffer (DLC register and data register), list of........................................................... 269 message buffer (ID register), list of ...................... 266 message buffer (x), procedure for reception by ... 315 message buffer (x), procedure for transmission by .......................................... 313 message buffer valid register (BVALR) ................ 283 mode data .............................................................. 96 mode pin ................................................................ 95 mode setting bit...................................................... 96 multi-byte data, accessing...................................... 24 multi-level message buffer, setting configuration of .......................................... 317 multiple interrupt..................................................... 53 N negative clock operation ...................................... 259 O operation, note on .................................................. 66 oscillation stabilization wait time, setting.......... 87, 89 output compare .................................................... 127 output compare (2 channels per one module) ..... 118 output compare block diagram............................. 127 output compare register ....................................... 128 output compare register 0, clearing counter upon match with.................................................. 126 output compare timing ......................................... 133 output compare, control status register of............ 129 output data register (UODR) ................................ 225 overflow, clearing counter by ............................... 125 P package dimension .................................................. 7 parity bit ............................................................... 234 pin assignment......................................................... 6 pin function............................................................... 8 PLL clock and main clock , switching between ...... 91 port data register.................................................. 102 port direction register ........................................... 103 PPG0 operation mode control register (PPGC0) . 168 PPG0, 1 clock select register (PPG01)................ 172 PPG1 operation mode control register (PPGC1) . 170 prefix code ............................................................. 37 prefix code, consecutive ........................................ 37 prefix instruction..................................................... 37 prefix instruction, restriction on interrupt disable instruction and ............................................. 37 processor status (PS) ............................................ 29 program counter (PC) ............................................ 32 PWM control 0 register ........................................ 322 PWM1&2 compare register.................................. 323 PWM1&2 select register ...................................... 324 R rate and data register (URD) content................... 226 read access, data read by.................................... 460 read state, setting flash memory to...................... 366 receive and transmit error counter (RTEC).......... 280 receive overrun .................................................... 308 receive overrun register (ROVRR)....................... 293 received message, storing ................................... 307 reception complete register (RCR) ...................... 291
472
INDEX reception interrupt enable register (RIER) ........... 294 recommended setting ............................................ 97 register bank .......................................................... 33 register bank pointer (RP)...................................... 30 reload value and pulse width, relationship between 8/16-bit PPG .............................................. 176 remote frame receiving wait register (RFWTR) ... 287 remote frame, processing for reception of ........... 308 remote request receiving register (RRTRR) ........ 292 request level setting register ................................ 187 reset cause ............................................................ 73 reset cause occurrence.......................................... 71 reset release, operation after ................................. 71 reset sequence .................................................... 342 reset state, setting flash memory to ..................... 366 ROM correction address register 0/1 (PADR0/PADR1) ....................................... 338 ROM correction control register (PACSR) ........... 339 ROM correction, block diagram of ....................... 338 ROM correction, operations of ............................. 339 ROM mirroring module, block diagram of ............ 346 ROM mirroring register (ROMM).......................... 347 RST and RY/BY timing ........................................ 463 RY/BY timing during writing/erasing .................... 462 S sector configuration.............................................. 351 sector erase timer flag (DQ3)............................... 364 sector, restarting erasing of flash memory........... 373 sector, suspending erasing of flash memory ....... 372 serial I/O operation....................................... 252, 254 serial I/O prescaler (CDCR) ................................. 251 serial mode control register (UMC) content ......... 221 serial mode control register (UMC), layout of ...... 221 serial mode control status register (SMCS) ......... 246 serial shift data register (SDR)............................. 250 serial write connection (power supplied from writer), example of ................................................. 387 serial write connection (user power supply used), example of ................................................. 385 serial write connection, basic configuration of ..... 382 set timing of six flags............................................ 235 setting ID.............................................................. 311 single mode.......................................................... 206 single mode, starting EI2OS in............................. 209 sleep mode, releasing............................................ 85 sleep mode, transition to........................................ 85 software interrupt ............................................. 40, 54 software interrupt operation....................................54 sound control register ...........................................330 sound generator register ......................................329 sound generator, block diagram of .......................328 special register .......................................................25 status flag during transmit and receive operation.239 status register (USR) content ...............................223 status register (USR) layout .................................223 stepping motor controller register .........................321 stepping motor controller, block diagram of..........320 stop mode.............................................................206 stop mode, releasing ..............................................87 stop mode, starting EI2OS in ................................213 stop mode, transition to ..........................................87 structure..................................................................57 sub-second register ..............................................160 system stack pointer (SSP), user stack pointer (USP) and.....................................................28 T time base counter .................................................109 time base timer control register (TBTC) ...............107 time base timer, block diagram of.........................106 time base timer, outline of ....................................106 timer control register.............................................158 timer control register (TMSCR), register content of....................................................145 timer control register (TMSCR), register layout of 145 timer mode, releasing .............................................86 timer mode, transition to .........................................86 timing limit exceeded flag (DQ5) ..........................363 toggle bit ...............................................................462 toggle bit flag (DQ6) .............................................362 tone count register................................................335 transfer data format ..............................................233 transmission cancel register (TCANR) .................288 transmission complete register (TCR) ..................289 transmission interrupt enable register (TIER).......290 transmission request register (TREQR) ...............285 transmission RTR register (TRTRR) ....................286 U undefined instruction, exception due to execution of ..................................................64 undefined instruction, execution of .........................64 user power supply ........................................385, 389 user stack pointer (USP) and system stack pointer (SSP)................................................28
473
INDEX W watch-dog counter................................................ 115 watch-dog stop..................................................... 115 watch-dog timer block diagram ............................ 112 watch-dog timer control register (WDTC)............. 113 watch-dog timer register....................................... 157 watch-dog timer, block diagram of ....................... 156 WE control ........................................................... 460 write data polling read (CE control)...................... 461 write, data polling, read (WE control)................... 460 writer ............................................................ 387, 391 writing to flash memory ........................................ 350
474
CM44-10105-2E
FUJITSU SEMICONDUCTOR * CONTROLLER MANUAL F2MC-16LX FAMILY 16-BIT MICROCONTROLLER Type MB90590 SERIES HARDWARE MANUAL
November 1999 the second edition
Published Edited
FUJITSU LIMITED
Electronic Devices
Technical Communication Dept.
FUJITSU SEMICONDUCTOR
FMC-16LX FAMILY 16-BIT MICROCONTROLLER MB90590 SERIES HARDWARE MANUAL


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